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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system

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This commit is contained in:
Matthias Jung
2014-07-15 22:49:33 +02:00
parent 8b4e3fa4bf dc9d1b4b1f
commit 793cf882fe
15 changed files with 63 additions and 168 deletions
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4
analyzer/analyzer/evaluationtool.cpp
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@@ -85,7 +85,7 @@ void EvaluationTool::runTests()
{
QString resourcesAbsPath = QApplication::applicationDirPath() + this->resourcesRelPath;
qDebug() << resourcesAbsPath;
PythonCaller pythonCaller(this->resourcesRelPath);
PythonCaller pythonCaller(resourcesAbsPath);
ui->traceTestTreeWidget->clear();
ui->testLight->setGray();
@@ -120,7 +120,7 @@ void EvaluationTool::calculateMetrics()
{
QString resourcesAbsPath = QApplication::applicationDirPath() + this->resourcesRelPath;
qDebug() << resourcesAbsPath;
PythonCaller pythonCaller(this->resourcesRelPath);
PythonCaller pythonCaller(resourcesAbsPath);
ui->traceMetricTreeWidget->clear();
for(int row = 0; row < traceFilesModel->rowCount(); ++row)
{

6
analyzer/analyzer/paths.pro
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@@ -8,6 +8,8 @@ CONFIG(qwt){
CONFIG(python){
LIBS += -lpython3.4m
INCLUDEPATH += /opt/python/include/python3.4m
# LIBS += -L/opt/python/lib -lpython3.4m
# INCLUDEPATH += /opt/python/include/python3.4m
LIBS += -lpython3.3m
INCLUDEPATH += /usr/include/python3.3
}

4
dram/resources/configs/amconfigs/am_wideio.xml
View File

@@ -11,10 +11,10 @@
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<addressmap>
<channel from="27" to="28" />
<row from="14" to="26" />
<colum from="7" to="13" />
<column from="7" to="13" />
<bank from="4" to="6" />
<bytes from="0" to="3" />
</addressmap>

2
dram/resources/simulations/sim-batch.xml
View File

@@ -16,7 +16,7 @@
<trace-setup id="media">
<device>mediabench-epic_32.stl</device>
<device clkMhz="800">mediabench-epic_32.stl</device>
</trace-setup>
</trace-setups>

120
dram/src/common/xmlAddressdecoder.cpp
View File

@@ -9,113 +9,31 @@ string xmlAddressDecoder::addressConfigURI = "";
xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI)
{
doc = new XMLDocument();
loadXML(addressConfigURI,*doc);
addressmap = doc->FirstChildElement("dramconfig")->FirstChildElement("addressmap");
int from;
int to;
tinyxml2::XMLDocument doc;
// get channel:
// TiXmlElement* channel = addressmap->FirstChildElement("channel");
//
//
// from = getAttribute<unsigned int>(channel, "from");
// to = getAttribute<unsigned int>(channel, "to");
//
// channelShift = from;
// channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
// channelSize = pow(2.0, to - from + 1.0);
loadXML(addressConfigURI, doc);
tinyxml2::XMLElement* addressmap = doc.FirstChildElement("dramconfig")->FirstChildElement("addressmap");
// get row:
XMLElement* row = addressmap->FirstChildElement("row");
row->QueryIntAttribute("from",&from);
row->QueryIntAttribute("to",&to);
for(XMLElement* child = addressmap->FirstChildElement(); child != NULL; child = child->NextSiblingElement())
{
int from;
int to;
rowShift = from;
rowMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
rowSize = pow(2.0, to - from + 1.0);
// get bank:
XMLElement* bank = addressmap->FirstChildElement("bank");
bank->QueryIntAttribute("from",&from);
bank->QueryIntAttribute("to",&to);
bankShift = from;
bankMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
bankSize = pow(2.0, to - from + 1.0);
// get colum:
XMLElement* colum = addressmap->FirstChildElement("colum");
colum->QueryIntAttribute("from",&from);
colum->QueryIntAttribute("to",&to);
columShift = from;
columMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
columSize = pow(2.0, to - from + 1.0);
// get bytes:
// TiXmlElement* bytes = addressmap->FirstChildElement("bytes");
//
// from = getAttribute<unsigned int>(bytes, "from");
// to = getAttribute<unsigned int>(bytes, "to");
// bytesShift = from;
// bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
// bytesSize = pow(2.0, to - from + 1.0);
child->QueryAttribute("from", &from);
child->QueryAttribute("to", &to);
shifts[child->Name()] = from;
masks[child->Name()] = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
}
}
xmlAddressDecoder::~xmlAddressDecoder()
DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
{
delete doc;
}
void xmlAddressDecoder::getNode(unsigned int addr, node * n)
{
n->channel = 0;
n->row = (addr & rowMask) >> rowShift;
n->bank = (addr & bankMask) >> bankShift;
n->colum = (addr & columMask) >> columShift;
}
void xmlAddressDecoder::getBRC(unsigned int addr, unsigned int &bank, unsigned int &row,
unsigned int &colum)
{
row = (addr & rowMask) >> rowShift;
bank = (addr & bankMask) >> bankShift;
colum = (addr & columMask) >> columShift;
}
void xmlAddressDecoder::getCBRC(unsigned int addr, unsigned int &channel, unsigned int &bank,
unsigned int &row, unsigned int &colum)
{
channel = (addr & channelMask) >> channelShift;
getBRC(addr, bank, row, colum);
}
void xmlAddressDecoder::getC(unsigned int addr, unsigned int &channel)
{
channel = (addr & channelMask) >> channelShift;
}
unsigned int xmlAddressDecoder::getNumberOfBanks()
{
return bankSize;
}
unsigned int xmlAddressDecoder::getNumberOfRowsPerBank()
{
return rowSize;
}
unsigned int xmlAddressDecoder::getNumberOfColumsPerRow()
{
return columSize;
}
unsigned int xmlAddressDecoder::getNumberOfBytesPerColumn()
{
return 1;
DecodedAddress n;
n.channel = 0;
n.row = (addr & masks["row"]) >> shifts["row"];
n.bank = (addr & masks["bank"]) >> shifts["bank"];
n.column = (addr & masks["column"]) >> shifts["column"];
return n;
}

43
dram/src/common/xmlAddressdecoder.h
View File

@@ -18,17 +18,20 @@
#include <sstream>
#include <string>
#include <math.h>
#include <map>
#include "third_party/tinyxml2.h"
struct node
struct DecodedAddress
{
DecodedAddress():channel(0),rank(0),bankgroup(0),row(0),bank(0),column(0),bytes(0){}
unsigned int channel;
unsigned int rank;
unsigned int bankgroup;
unsigned int row;
unsigned int bank;
unsigned int colum;
tlm::tlm_command command;
tlm::tlm_phase phase;
unsigned int column;
unsigned int bytes;
};
class xmlAddressDecoder
@@ -43,39 +46,13 @@ public:
return decoder;
}
void getNode(unsigned int addr, node * n);
void getBRC(unsigned int addr, unsigned int &bank, unsigned int &row, unsigned int &colum);
void getCBRC(unsigned int addr, unsigned int &channel, unsigned int &bank, unsigned int &row, unsigned int &colum);
void getC(unsigned int addr, unsigned int &channel);
unsigned int getNumberOfBanks();
unsigned int getNumberOfRowsPerBank();
unsigned int getNumberOfColumsPerRow();
unsigned int getNumberOfBytesPerColumn();
DecodedAddress decodeAddress(sc_dt::uint64 addr);
private:
xmlAddressDecoder(std::string URI);
~xmlAddressDecoder();
unsigned int channelMask;
unsigned int rowMask;
unsigned int bankMask;
unsigned int columMask;
unsigned int bytesMask;
unsigned int channelShift;
unsigned int rowShift;
unsigned int bankShift;
unsigned int columShift;
unsigned int bytesShift;
unsigned int channelSize;
unsigned int bankSize;
unsigned int rowSize;
unsigned int columSize;
unsigned int bytesSize;
tinyxml2::XMLDocument * doc;
tinyxml2::XMLElement* addressmap;
std::map<std::string, sc_dt::uint64> masks;
std::map<std::string, unsigned int> shifts;
};
#endif

13
dram/src/controller/core/ControllerState.cpp
View File

@@ -63,15 +63,9 @@ const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank)
void ControllerState::change(const ScheduledCommand& scheduledCommand)
{
//TODO double check if slot free?
bus.blockSlot(scheduledCommand.getStart());
// if(getLastCommand(scheduledCommand.getCommand()).getStart() > scheduledCommand.getStart())
// cout << commandToString(scheduledCommand.getCommand()) << " wurde vorgezogen! " << std::endl;
lastScheduledByCommandAndBank[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand;
//lastScheduledByBank[scheduledCommand.getCommand()] = scheduledCommand;
switch (scheduledCommand.getCommand())
{
@@ -107,10 +101,6 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand)
default:
break;
}
// cout << "Last Data Strobe Commands Size: " << lastDataStrobeCommands.size() << std::endl;
// cout << "Last Activates Size: " << lastActivates.size() << std::endl;
// cout << "Bus Slots: " << bus.slotSet.size();
}
void ControllerState::cleanUp(sc_time time)
@@ -123,7 +113,8 @@ void ControllerState::cleanUp(sc_time time)
tmp.push_back(command);
}
lastDataStrobeCommands = tmp;
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory()));
if(time >= config->Timings.tActHistory())
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory()));
}
} /* namespace controller */

5
dram/src/controller/core/TimingCalculation.cpp
View File

@@ -23,6 +23,11 @@ sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constr
return SC_ZERO_TIME;
}
const sc_time FrequencyToClk(double frequencyMhz)
{
return sc_time(1 / frequencyMhz, SC_US);
}
const sc_time clkAlign(sc_time time, Alignment alignment)
{
sc_time clk = Configuration::getInstance().Timings.clk;

1
dram/src/controller/core/TimingCalculation.h
View File

@@ -26,6 +26,7 @@ sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constr
enum Alignment {UP, DOWN};
const sc_time clkAlign(sc_time time, Alignment alignment = UP);
bool isClkAligned(sc_time time, sc_time clk);
const sc_time FrequencyToClk(double frequencyMhz);
}

6
dram/src/controller/core/configuration/MemSpecLoader.cpp
View File

@@ -7,6 +7,7 @@
#include "MemSpecLoader.h"
#include "TimingConfiguration.h"
#include "../TimingCalculation.h"
using namespace tinyxml2;
using namespace std;
@@ -91,9 +92,8 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
//MemTimings
XMLElement* timings = memspec->FirstChildElement("memtimingspec");
double clkMhz = queryDoubleParameter(timings, "clkMhz");
sc_time clk = sc_time(1 / clkMhz, SC_US);
config.Timings.clk = clk;
config.Timings.clk = FrequencyToClk(clkMhz);
sc_time clk = config.Timings.clk;
config.Timings.tRP = clk * queryUIntParameter(timings, "RP");
config.Timings.tRAS = clk * queryUIntParameter(timings, "RAS");
config.Timings.tRC = clk * queryUIntParameter(timings, "RC");

5
dram/src/simulation/Arbiter.h
View File

@@ -135,10 +135,9 @@ private:
void appendDramExtension(int socketId, tlm_generic_payload& payload)
{
unsigned int burstlength = payload.get_streaming_width();
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DecodedAddress n = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address());
Bank bank(n.bank);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), bank, bank.getBankGroup(), Row(n.row), Column(n.colum),burstlength);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), bank, bank.getBankGroup(), Row(n.row), Column(n.column),burstlength);
payload.set_auto_extension(extension);
}
};

8
dram/src/simulation/Simulation.cpp
View File

@@ -83,10 +83,10 @@ void Simulation::instantiateModules(const string &pathToResources, const std::ve
arbiter = new Arbiter<NumberOfTracePlayers, 128>("arbiter");
controller = new Controller<>("controller");
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].burstLength, this);
player3 = new TracePlayer<>("player3", pathToResources + string("traces/") + devices[2].trace, devices[2].burstLength, this);
player4 = new TracePlayer<>("player4", pathToResources + string("traces/") + devices[3].trace, devices[3].burstLength, this);
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, devices[0].clk, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].burstLength, devices[1].clk, this);
player3 = new TracePlayer<>("player3", pathToResources + string("traces/") + devices[2].trace, devices[2].burstLength, devices[2].clk, this);
player4 = new TracePlayer<>("player4", pathToResources + string("traces/") + devices[3].trace, devices[3].burstLength, devices[3].clk, this);
}
void Simulation::bindSockets()

3
dram/src/simulation/Simulation.h
View File

@@ -30,10 +30,11 @@ struct DramSetup
struct Device
{
Device():trace("empty.stl"), burstLength(0){}
Device(std::string trace, unsigned int burstLength = 8) : trace(trace), burstLength(burstLength)
Device(std::string trace, sc_time clk, unsigned int burstLength = 8) : trace(trace), clk (clk), burstLength(burstLength)
{
}
std::string trace;
sc_time clk;
unsigned int burstLength;
};

2
dram/src/simulation/SimulationManager.cpp
View File

@@ -149,7 +149,7 @@ void SimulationManager::addTraceSetup(SimulationBatch& batch, tinyxml2::XMLEleme
vector<Device> devices;
for (XMLElement* device = element->FirstChildElement("device"); device != NULL; device = device->NextSiblingElement("device"))
{
devices.push_back(Device(device->GetText(), device->IntAttribute("bl")));
devices.push_back(Device(device->GetText(), FrequencyToClk(device->DoubleAttribute("clkMhz")), device->IntAttribute("bl")));
}
while (devices.size() < Simulation::NumberOfTracePlayers)
{

9
dram/src/simulation/TracePlayer.h
View File

@@ -31,7 +31,7 @@ struct TracePlayer: public sc_module
{
public:
tlm_utils::simple_initiator_socket<TracePlayer, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
TracePlayer(sc_module_name /*name*/, string pathToTrace, unsigned int burstLength,
TracePlayer(sc_module_name /*name*/, string pathToTrace, unsigned int burstLength, sc_time clk,
simulation::ISimulation* simulationManager);
void start();
@@ -46,6 +46,7 @@ private:
MemoryManager memoryManager;
ifstream file;
unsigned int burstlenght;
sc_time clk;
unsigned int numberOfPendingTransactions;
unsigned int transactionsSent;
unsigned int transactionsReceived;
@@ -54,8 +55,8 @@ private:
template<unsigned int BUSWIDTH>
TracePlayer<BUSWIDTH>::TracePlayer(sc_module_name, string pathToTrace, unsigned int burstLength, simulation::ISimulation *simulationManager) :
payloadEventQueue(this, &TracePlayer<BUSWIDTH>::peqCallback), file(pathToTrace), burstlenght(burstLength),
TracePlayer<BUSWIDTH>::TracePlayer(sc_module_name, string pathToTrace, unsigned int burstLength, sc_time clk, simulation::ISimulation *simulationManager) :
payloadEventQueue(this, &TracePlayer<BUSWIDTH>::peqCallback), file(pathToTrace), burstlenght(burstLength), clk(clk),
numberOfPendingTransactions(0), transactionsSent(0), transactionsReceived(0), simulationManager(simulationManager)
{
if (!file.is_open())
@@ -112,7 +113,7 @@ void TracePlayer<BUSWIDTH>::generateNextPayload()
payload->set_byte_enable_length(0);
payload->set_streaming_width(burstlenght);
sc_time sendingTime = sc_time(std::stoi(time.c_str()), SC_NS);
sc_time sendingTime = std::stoi(time.c_str())*clk;
GenerationExtension* genExtension = new GenerationExtension(sendingTime);
payload->set_auto_extension(genExtension);