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bankgroup in dram extension

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This commit is contained in:
Janik Schlemminger
2014-04-09 21:22:42 +02:00
parent 93bc1edb82
commit d6825125e1
10 changed files with 171 additions and 74 deletions
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2
dram/resources/configs/memconfigs/memconfig.xml
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@@ -4,7 +4,7 @@
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="100" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>

157
dram/src/common/dramExtension.h
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@@ -13,52 +13,83 @@
class Thread
{
public :
explicit Thread(unsigned int id) : id(id) {}
public:
explicit Thread(unsigned int id) :
id(id)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Channel
{
public :
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit Channel(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class BankGroup
{
public :
explicit BankGroup(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit BankGroup(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Bank
{
public :
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit Bank(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Row
{
public :
public:
static const Row NO_ROW;
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
Row() :
id(0), isNoRow(true)
{
}
explicit Row(unsigned int id) :
id(id), isNoRow(false)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
bool isNoRow;
@@ -68,10 +99,16 @@ private:
class Column
{
public :
explicit Column(unsigned int id) : id(id) {}
public:
explicit Column(unsigned int id) :
id(id)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -95,50 +132,90 @@ bool operator!=(const Row &lhs, const Row &rhs);
bool operator==(const Column &lhs, const Column &rhs);
bool operator!=(const Column &lhs, const Column &rhs);
class DramExtension : public tlm::tlm_extension<DramExtension>
class DramExtension: public tlm::tlm_extension<DramExtension>
{
private:
Thread thread;
Channel channel;
Bank bank;
Row row;
BankGroup bankgroup;
Row row;
Column column;
unsigned int burstlength;
public:
DramExtension():thread(0),channel(0),bank(0),row(0),column(0),burstlength(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(0),bank(bank),row(row),column(column), burstlength(burstlength){}
DramExtension(const Thread& thread,const Channel& channel, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(channel),bank(bank),row(row),column(column), burstlength(burstlength){}
DramExtension() :
thread(0), channel(0), bank(0), bankgroup(0), row(0), column(0), burstlength(0)
{
}
DramExtension(const Thread& thread, const Bank& bank, const BankGroup& bankgroup,
const Row& row, const Column& column, unsigned int burstlength = 0) :
thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row), column(column), burstlength(
burstlength)
{
}
DramExtension(const Thread& thread, const Channel& channel, const Bank& bank,
const BankGroup& bankgroup, const Row& row, const Column& column,
unsigned int burstlength = 0) :
thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row), column(
column), burstlength(burstlength)
{
}
~DramExtension(){}
~DramExtension()
{
}
virtual tlm_extension_base* clone() const
{
return new DramExtension(thread, bank, row, column, burstlength);
return new DramExtension(thread, bank, bankgroup, row, column, burstlength);
}
virtual void copy_from(const tlm_extension_base& ext)
{
const DramExtension& cpyFrom = static_cast<const DramExtension&>(ext);
thread = cpyFrom.thread;
bank = cpyFrom.bank;
bankgroup = cpyFrom.bankgroup;
row = cpyFrom.row;
column = cpyFrom.column;
burstlength = cpyFrom.burstlength;
}
const Thread& getThread() const{return thread;}
const Channel& getChannel() const{return channel;}
const Bank& getBank() const{return bank;}
const Row& getRow() const{return row;}
const Column& getColumn() const{return column;}
const unsigned int getBurstlength() const{return burstlength;}
const Thread& getThread() const
{
return thread;
}
const Channel& getChannel() const
{
return channel;
}
const Bank& getBank() const
{
return bank;
}
const BankGroup& getBankGroup() const
{
return bankgroup;
}
const Row& getRow() const
{
return row;
}
const Column& getColumn() const
{
return column;
}
const unsigned int getBurstlength() const
{
return burstlength;
}
void setRow(const Row& row){this->row = row;}
void setRow(const Row& row)
{
this->row = row;
}
static DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload &payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload &payload);
};
#endif /* DRAMEXTENSION_H_ */

10
dram/src/core/powerdown/PowerDownManager.cpp
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@@ -8,6 +8,7 @@
#include "PowerDownManager.h"
#include "../ControllerCore.h"
#include "../../common/Utils.h"
#include "../utils/Utils.h"
using namespace tlm;
@@ -251,14 +252,7 @@ void PowerDownManager::init()
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = powerDownPayloads[bank];
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(payload, bank);
//send payload
ScheduledCommand pdn(Command::PDNP, SC_ZERO_TIME, SC_ZERO_TIME,

11
dram/src/core/refresh/RefreshManager.cpp
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@@ -7,6 +7,7 @@
#include "RefreshManager.h"
#include "../ControllerCore.h"
#include "../utils/Utils.h"
using namespace tlm;
namespace core {
@@ -92,15 +93,7 @@ void RefreshManager::setupTransactions()
{
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = refreshPayloads.at(bank.ID());
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(refreshPayloads.at(bank.ID()), bank);
}
}

9
dram/src/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -115,14 +115,7 @@ bool RefreshManagerBankwise::RefreshManagerForBank::isInvalidated(sc_time time)
void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction()
{
refreshPayload.set_address(getStartAddress(bank));
refreshPayload.set_command(tlm::TLM_READ_COMMAND);
refreshPayload.set_data_length(0);
refreshPayload.set_response_status(tlm::TLM_OK_RESPONSE);
refreshPayload.set_dmi_allowed(false);
refreshPayload.set_byte_enable_length(0);
refreshPayload.set_streaming_width(0);
refreshPayload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(refreshPayload, bank);
}
void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)

12
dram/src/core/utils/Utils.cpp
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@@ -83,3 +83,15 @@ sc_time core::getBurstLengthOnDataStrobe(unsigned int burstlength)
return config.Timings.clk * (burstlength / config.DataRate);
}
void core::setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank)
{
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, getBankGroup(bank), Row(0), Column(0))); //payload takes ownership
}

2
dram/src/core/utils/Utils.h
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@@ -39,5 +39,7 @@ bool isClkAligned(sc_time time, sc_time clk);
BankGroup getBankGroup(Bank bank);
void setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank);
};
#endif /* UTILS_H_ */

3
dram/src/simulation/Arbiter.h
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@@ -17,6 +17,7 @@
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../common/xmlAddressdecoder.h"
#include "../common/dramExtension.h"
#include "../core/utils/Utils.h"
#include <iostream>
@@ -135,7 +136,7 @@ private:
unsigned int burstlength = payload.get_streaming_width();
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), Row(n.row), Column(n.colum),burstlength);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), core::getBankGroup(Bank(n.bank)), Row(n.row), Column(n.colum),burstlength);
payload.set_auto_extension(extension);
}
};

29
dram/src/simulation/Controller.h
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@@ -207,6 +207,8 @@ private:
Scheduler* scheduler;
std::map<Bank, int> numberOfPayloadsInSystem;
tlm::tlm_generic_payload* backpressure = NULL;
tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> dramPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> controllerPEQ;
@@ -214,6 +216,16 @@ private:
sc_time inputBufferDelay;
DebugManager& debugManager;
unsigned int getNumberOfPayloadsInSystem()
{
unsigned int sum = 0;
for(Bank bank : controller->getBanks())
{
sum += numberOfPayloadsInSystem[bank];
}
return sum;
}
void payloadEntersSystem(tlm_generic_payload& payload)
{
Bank bank = DramExtension::getExtension(payload).getBank();
@@ -296,11 +308,26 @@ private:
if (phase == BEGIN_REQ)
{
payload.acquire();
if(getNumberOfPayloadsInSystem() == controller->config.MaxNrOfTransactions)
{
printDebugMessage("##Backpressure: Max number of transactions in system reached");
backpressure = &payload;
return TLM_ACCEPTED;
}
payloadEntersSystem(payload);
frontendPEQ.notify(payload, phase, inputBufferDelay);
}
else if (phase == END_RESP)
{
if(backpressure != NULL)
{
payloadEntersSystem(*backpressure);
frontendPEQ.notify(*backpressure, BEGIN_REQ, inputBufferDelay);
backpressure = NULL;
}
payloadLeavesSystem(payload);
payload.release();
}
@@ -335,13 +362,11 @@ private:
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
}
else if (phase == END_RDA || phase == END_WRA)
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
scheduleNextPayload(bank);
}
else if (isIn(phase, { BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL, BEGIN_RDA, BEGIN_WRA }))

10
dram/src/simulation/main.cpp
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@@ -35,13 +35,13 @@ int sc_main(int argc, char **argv)
string memconfig = "memconfig.xml";
string memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
// string memspec = "MatzesWideIO.xml";
// memspec = "MatzesWideIO.xml";
string stl1 = "chstone-sha_32.stl";
stl1 = "empty.stl";
unsigned int burstlength1 = 4;
//stl1 = "empty.stl";
unsigned int burstlength1 = 8;
string stl2 = "mediabench-h263decode_32.stl";
// stl2 = "trace.stl";
unsigned int burstlength2 = 4;
stl2 = "trace.stl";
unsigned int burstlength2 = 8;
string traceName = "tpr.tdb";
SimulationManager simulationManager("sim",memconfig,memspec,stl1,burstlength1, stl2,burstlength2, traceName, resources,false);