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resolved conflict

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This commit is contained in:
robert
2014-04-10 00:05:25 +02:00
parent 76ebfb2dd8 d840cc7fd1
commit 7c31ee8ee1
14 changed files with 341 additions and 120 deletions
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2
dram/.cproject
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@@ -80,7 +80,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="src|testing" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="testing|src" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src/common"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src/core"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src/scheduler"/>

6
dram/resources/configs/memconfigs/memconfig.xml
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@@ -3,9 +3,9 @@
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="100" />
<parameter id="scheduler" type="string" value="FIFO" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

157
dram/src/common/dramExtension.h
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@@ -13,52 +13,83 @@
class Thread
{
public :
explicit Thread(unsigned int id) : id(id) {}
public:
explicit Thread(unsigned int id) :
id(id)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Channel
{
public :
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit Channel(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class BankGroup
{
public :
explicit BankGroup(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit BankGroup(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Bank
{
public :
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
public:
explicit Bank(unsigned int id) :
id(id)
{
}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class Row
{
public :
public:
static const Row NO_ROW;
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
Row() :
id(0), isNoRow(true)
{
}
explicit Row(unsigned int id) :
id(id), isNoRow(false)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
bool isNoRow;
@@ -68,10 +99,16 @@ private:
class Column
{
public :
explicit Column(unsigned int id) : id(id) {}
public:
explicit Column(unsigned int id) :
id(id)
{
}
unsigned int ID() const { return id;}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -96,50 +133,90 @@ bool operator!=(const Row &lhs, const Row &rhs);
bool operator==(const Column &lhs, const Column &rhs);
bool operator!=(const Column &lhs, const Column &rhs);
class DramExtension : public tlm::tlm_extension<DramExtension>
class DramExtension: public tlm::tlm_extension<DramExtension>
{
private:
Thread thread;
Channel channel;
Bank bank;
Row row;
BankGroup bankgroup;
Row row;
Column column;
unsigned int burstlength;
public:
DramExtension():thread(0),channel(0),bank(0),row(0),column(0),burstlength(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(0),bank(bank),row(row),column(column), burstlength(burstlength){}
DramExtension(const Thread& thread,const Channel& channel, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(channel),bank(bank),row(row),column(column), burstlength(burstlength){}
DramExtension() :
thread(0), channel(0), bank(0), bankgroup(0), row(0), column(0), burstlength(0)
{
}
DramExtension(const Thread& thread, const Bank& bank, const BankGroup& bankgroup,
const Row& row, const Column& column, unsigned int burstlength = 0) :
thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row), column(column), burstlength(
burstlength)
{
}
DramExtension(const Thread& thread, const Channel& channel, const Bank& bank,
const BankGroup& bankgroup, const Row& row, const Column& column,
unsigned int burstlength = 0) :
thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row), column(
column), burstlength(burstlength)
{
}
~DramExtension(){}
~DramExtension()
{
}
virtual tlm_extension_base* clone() const
{
return new DramExtension(thread, bank, row, column, burstlength);
return new DramExtension(thread, bank, bankgroup, row, column, burstlength);
}
virtual void copy_from(const tlm_extension_base& ext)
{
const DramExtension& cpyFrom = static_cast<const DramExtension&>(ext);
thread = cpyFrom.thread;
bank = cpyFrom.bank;
bankgroup = cpyFrom.bankgroup;
row = cpyFrom.row;
column = cpyFrom.column;
burstlength = cpyFrom.burstlength;
}
const Thread& getThread() const{return thread;}
const Channel& getChannel() const{return channel;}
const Bank& getBank() const{return bank;}
const Row& getRow() const{return row;}
const Column& getColumn() const{return column;}
const unsigned int getBurstlength() const{return burstlength;}
const Thread& getThread() const
{
return thread;
}
const Channel& getChannel() const
{
return channel;
}
const Bank& getBank() const
{
return bank;
}
const BankGroup& getBankGroup() const
{
return bankgroup;
}
const Row& getRow() const
{
return row;
}
const Column& getColumn() const
{
return column;
}
const unsigned int getBurstlength() const
{
return burstlength;
}
void setRow(const Row& row){this->row = row;}
void setRow(const Row& row)
{
this->row = row;
}
static DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload &payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension& getExtension(const tlm::tlm_generic_payload &payload);
};
#endif /* DRAMEXTENSION_H_ */

10
dram/src/core/powerdown/PowerDownManager.cpp
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@@ -8,6 +8,7 @@
#include "PowerDownManager.h"
#include "../ControllerCore.h"
#include "../../common/Utils.h"
#include "../utils/Utils.h"
using namespace tlm;
@@ -251,14 +252,7 @@ void PowerDownManager::init()
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = powerDownPayloads[bank];
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(payload, bank);
//send payload
ScheduledCommand pdn(Command::PDNP, SC_ZERO_TIME, SC_ZERO_TIME,

11
dram/src/core/refresh/RefreshManager.cpp
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@@ -7,6 +7,7 @@
#include "RefreshManager.h"
#include "../ControllerCore.h"
#include "../utils/Utils.h"
using namespace tlm;
namespace core {
@@ -92,15 +93,7 @@ void RefreshManager::setupTransactions()
{
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = refreshPayloads.at(bank.ID());
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(refreshPayloads.at(bank.ID()), bank);
}
}

9
dram/src/core/refresh/RefreshManagerBankwise.cpp
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@@ -115,14 +115,7 @@ bool RefreshManagerBankwise::RefreshManagerForBank::isInvalidated(sc_time time)
void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction()
{
refreshPayload.set_address(getStartAddress(bank));
refreshPayload.set_command(tlm::TLM_READ_COMMAND);
refreshPayload.set_data_length(0);
refreshPayload.set_response_status(tlm::TLM_OK_RESPONSE);
refreshPayload.set_dmi_allowed(false);
refreshPayload.set_byte_enable_length(0);
refreshPayload.set_streaming_width(0);
refreshPayload.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership
setUpDummy(refreshPayload, bank);
}
void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)

12
dram/src/core/utils/Utils.cpp
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@@ -83,3 +83,15 @@ sc_time core::getBurstLengthOnDataStrobe(unsigned int burstlength)
return config.Timings.clk * (burstlength / config.DataRate);
}
void core::setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank)
{
payload.set_address(getStartAddress(bank));
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, getBankGroup(bank), Row(0), Column(0))); //payload takes ownership
}

2
dram/src/core/utils/Utils.h
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@@ -39,5 +39,7 @@ bool isClkAligned(sc_time time, sc_time clk);
BankGroup getBankGroup(Bank bank);
void setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank);
};
#endif /* UTILS_H_ */

3
dram/src/simulation/Arbiter.h
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@@ -17,6 +17,7 @@
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../common/xmlAddressdecoder.h"
#include "../common/dramExtension.h"
#include "../core/utils/Utils.h"
#include <iostream>
@@ -135,7 +136,7 @@ private:
unsigned int burstlength = payload.get_streaming_width();
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), Row(n.row), Column(n.colum),burstlength);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), core::getBankGroup(Bank(n.bank)), Row(n.row), Column(n.colum),burstlength);
payload.set_auto_extension(extension);
}
};

29
dram/src/simulation/Controller.h
View File

@@ -217,6 +217,8 @@ private:
Scheduler* scheduler;
std::map<Bank, int> numberOfPayloadsInSystem;
tlm::tlm_generic_payload* backpressure = NULL;
tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> dramPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> controllerPEQ;
@@ -224,6 +226,16 @@ private:
sc_time inputBufferDelay;
DebugManager& debugManager;
unsigned int getNumberOfPayloadsInSystem()
{
unsigned int sum = 0;
for(Bank bank : controller->getBanks())
{
sum += numberOfPayloadsInSystem[bank];
}
return sum;
}
void payloadEntersSystem(tlm_generic_payload& payload)
{
Bank bank = DramExtension::getExtension(payload).getBank();
@@ -306,11 +318,26 @@ private:
if (phase == BEGIN_REQ)
{
payload.acquire();
if(getNumberOfPayloadsInSystem() == controller->config.MaxNrOfTransactions)
{
printDebugMessage("##Backpressure: Max number of transactions in system reached");
backpressure = &payload;
return TLM_ACCEPTED;
}
payloadEntersSystem(payload);
frontendPEQ.notify(payload, phase, inputBufferDelay);
}
else if (phase == END_RESP)
{
if(backpressure != NULL)
{
payloadEntersSystem(*backpressure);
frontendPEQ.notify(*backpressure, BEGIN_REQ, inputBufferDelay);
backpressure = NULL;
}
payloadLeavesSystem(payload);
payload.release();
}
@@ -345,13 +372,11 @@ private:
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
}
else if (phase == END_RDA || phase == END_WRA)
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
scheduleNextPayload(bank);
}
else if (isIn(phase, { BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL, BEGIN_RDA, BEGIN_WRA }))

38
dram/src/simulation/SimulationManager.cpp
View File

@@ -17,9 +17,8 @@ using namespace std;
namespace simulation {
SimulationManager::SimulationManager(sc_module_name name, string memconfig, string memspec,
string stl1, unsigned int burstlength1, string stl2, unsigned int burstlenght2,
string traceName, string pathToResources, bool silent) :
Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent) :
traceName(traceName)
{
@@ -28,16 +27,25 @@ SimulationManager::SimulationManager(sc_module_name name, string memconfig, stri
xmlAddressDecoder::addressConfigURI = pathToResources + string("configs/addressConfig.xml");
TlmRecorder::dbName = traceName;
TlmRecorder::sqlScriptURI = pathToResources + string("scripts/createTraceDB.sql");
Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + memconfig;
Configuration::memspecUri = pathToResources + string("configs/memspecs/") + memspec;
Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + setup.memconfig;
Configuration::memspecUri = pathToResources + string("configs/memspecs/") + setup.memspec;
//setup dram
dram = new Dram<>("dram");
arbiter = new Arbiter<numberOfTracePlayers,128>("arbiter");
arbiter = new Arbiter<numberOfTracePlayers, 128>("arbiter");
controller = new Controller<>("controller");
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + stl1, burstlength1,
this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + stl2, burstlenght2,
this);
//setup devices
for(auto& d : devices)
{
if(d.burstLength == 0)
d.burstLength = 8;
}
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace,
devices[0].burstLength, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace,
devices[1].burstLength, this);
player1->iSocket.bind(arbiter->tSockets[0]);
player2->iSocket.bind(arbiter->tSockets[1]);
@@ -58,7 +66,7 @@ SimulationManager::SimulationManager(sc_module_name name, string memconfig, stri
DebugManager::getInstance().addToWhiteList(whiteList);
}
SimulationManager::~SimulationManager()
Simulation::~Simulation()
{
delete dram;
delete arbiter;
@@ -67,10 +75,10 @@ SimulationManager::~SimulationManager()
delete player2;
}
void SimulationManager::startSimulation()
void Simulation::startSimulation()
{
clock_t begin = clock();
DebugManager::getInstance().printDebugMessage(name(), "Starting simulation");
@@ -84,7 +92,7 @@ void SimulationManager::startSimulation()
"Simulation took " + to_string(elapsed_secs) + " seconds");
}
void SimulationManager::tracePlayerFinishedCallback(string name)
void Simulation::tracePlayerFinishedCallback(string name)
{
DebugManager::getInstance().printDebugMessage(this->name(), "Traceplayer " + name + " finshed");
@@ -96,7 +104,7 @@ void SimulationManager::tracePlayerFinishedCallback(string name)
}
}
void SimulationManager::terminationThread()
void Simulation::terminationThread()
{
wait(terminateSimulation);
DebugManager::getInstance().printDebugMessage(this->name(), "Terminating simulation");

31
dram/src/simulation/SimulationManager.h
View File

@@ -18,15 +18,31 @@
namespace simulation {
class SimulationManager: public ISimulationManager, public sc_module
struct DramSetup
{
DramSetup():memconfig(""),memspec(""){}
DramSetup(std::string memconfig, std::string memspec) : memconfig(memconfig), memspec(memspec) {}
std::string memconfig;
std::string memspec;
};
struct Device
{
Device():trace("empty.stl"), burstLength(0){}
Device(std::string trace, unsigned int burstLength = 0) : trace(trace), burstLength(burstLength)
{
}
std::string trace;
unsigned int burstLength;
};
class Simulation: public ISimulationManager, public sc_module
{
public:
SC_HAS_PROCESS(SimulationManager);
SimulationManager(sc_module_name name, std::string memconfig, std::string memspec,
std::string stl1, unsigned int burstlength1, std::string stl2,
unsigned int burstlenght2, std::string traceName, std::string pathToResources,
bool silent = false);
~SimulationManager();
SC_HAS_PROCESS(Simulation);
Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent = false);
~Simulation();
void startSimulation();
void tracePlayerFinishedCallback(string name) override;
@@ -38,6 +54,7 @@ private:
Dram<> *dram;
Arbiter<numberOfTracePlayers, 128> *arbiter;
Controller<> *controller;
TracePlayer<> *player1;
TracePlayer<> *player2;
};

99
dram/src/simulation/main.cpp Normal file
View File

@@ -0,0 +1,99 @@
/*
* main.cpp
*
* Created on: Mar 16, 2014
* Author: robert
*/
#include <iostream>
#include <string>
#include "SimulationManager.h"
#include "../core/configuration/Configuration.h"
#include <systemc.h>
#include <sys/wait.h>
#include <utility>
#include <vector>
using namespace std;
using namespace simulation;
string resources;
string pathOfFile(string file)
{
return file.substr(0, file.find_last_of('/'));
}
void startTraceAnalyzer(string traceName)
{
string p = getenv("trace");
string run_tpr = p + " " + traceName;
system(run_tpr.c_str());
}
bool runSimulation(string resources, string traceName, DramSetup setup, vector<Device> devices)
{
int pid = fork();
int status = 0;
if (pid == 0)
{
Simulation simulation("sim", resources, traceName, setup, devices);
simulation.startSimulation();
return true;
}
waitpid(pid, &status, 0);
return false;
}
bool batchTraces(DramSetup setup, vector<pair<string, string>> tracePairs)
{
int id =0;
for(pair<string, string> pair : tracePairs)
{
id++;
string traceName = "batch" + to_string(id) + ".tdb";
if(runSimulation(resources, traceName, setup, { Device(pair.first), Device(pair.second) }))
return true;//kill child
}
}
bool batchSetups(pair<string, string >tracePair, vector<DramSetup> setups)
{
int id =0;
for(auto& setup : setups)
{
id++;
string traceName = "batch0" + to_string(id) + ".tdb";
if(runSimulation(resources, traceName, setup, { Device(tracePair.first), Device(tracePair.second) }))
return true;//kill child
}
}
int sc_main(int argc, char **argv)
{
sc_set_time_resolution(1, SC_PS);
resources = pathOfFile(argv[0]) + string("/../resources/");
DramSetup setup;
setup.memconfig = "memconfig.xml";
//setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
setup.memspec = "MatzesWideIO.xml";
DramSetup setup2;
setup2.memconfig = "memconfig.xml";
setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
vector<pair<string, string>> tracePairs;
tracePairs.push_back(pair<string, string>("trace.stl", "empty.stl"));
tracePairs.push_back(pair<string, string>("trace2.stl", "empty.stl"));
//batchTraces(setup, tracePairs);
batchSetups(tracePairs[0], {setup, setup2});
return 0;
}

52
dram/testing/main.cpp
View File

@@ -5,29 +5,29 @@
* Author: jonny
*/
#include <iostream>
#include <gtest/gtest.h>
#include <tlm.h>
#include <systemc.h>
#include <unistd.h>
#include <gtest/gtest.h>
#include <memory.h>
#include <set>
using namespace std;
using namespace testing;
int runTests(int argc, char **argv)
{
cout << "---- Starting Tests ----" <<endl;
InitGoogleTest(&argc, argv);
return RUN_ALL_TESTS();
}
int main(int argc, char **argv) {
return runTests(argc,argv);
}
int sc_main(int argc, char **argv) {
return main(argc,argv);
}
//#include <iostream>
//#include <gtest/gtest.h>
//#include <tlm.h>
//#include <systemc.h>
//#include <unistd.h>
//#include <gtest/gtest.h>
//#include <memory.h>
//#include <set>
//using namespace std;
//using namespace testing;
//
//
//int runTests(int argc, char **argv)
//{
// cout << "---- Starting Tests ----" <<endl;
// InitGoogleTest(&argc, argv);
// return RUN_ALL_TESTS();
//}
//
//int main(int argc, char **argv) {
// return runTests(argc,argv);
//}
//
//int sc_main(int argc, char **argv) {
// return main(argc,argv);
//}