Commit Graph

1003 Commits

Author SHA1 Message Date
Gabe Black
fda2e46a9e cpu: De-templatize the FullO3CPU class.
Change-Id: Ib7f1e40447a2f5a49e0c9a3af8579d075d5d3625
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
4ba06c8f25 cpu: Delete the unnecessary BaseO3CPU class.
This class has no content, and is not used for anything except as an
extra layer between FullO3CPU and BaseCPU.

Change-Id: Idb6258a655b0fb614e94b0fc0e281696d5081ab0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
157f9757c2 cpu: De-templatize the O3ThreadContext.
Change-Id: I1559760949031bd63bd3a48e62c37448c1f6f5b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42115
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
2021-05-21 01:19:37 +00:00
Gabe Black
e164d08287 cpu: De-templatize the O3 DefaultCommit.
Change-Id: I054cb344a5e3829caf6cbd26e931514b877c1577
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42114
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
fe65f1e864 cpu: De-templatize the O3 DefaultRename.
Change-Id: I28fbf5f3727c94ddf64a0e047784663508c6bda2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42113
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
03a843cf77 cpu: De-templatize the O3 DefaultIEW.
Change-Id: Ieb7b23250573a3bc7e7ff296ff6bf8811a865802
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
9722ce0075 cpu: De-templatize the O3 LSQ.
Change-Id: I7821fe971c0c38b77e730b4c40fb9fb204c6e7fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42111
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
da4c0590ee cpu: De-templatize the O3 DefaultDecode.
Change-Id: If2cef59654db4f5ff8e7cb73d1951895e5e12c9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42110
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
f4a3380167 cpu: De-templatize the O3 DefaultFetch.
Change-Id: I5d4ce7a269c9f1df497003404872a977e7edb575
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42109
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
9adca30528 cpu: De-templatize the O3 InstructionQueue.
Change-Id: Id897b66b4041a6be4c85019585b205e8d8b366e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42108
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 01:19:37 +00:00
Gabe Black
0f667aff1f cpu: De-templatize O3's LSQUnit.
Change-Id: Id426950b4fec9b98855b3f9f95e63fc0d9b6e64f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42107
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
2021-05-21 01:19:37 +00:00
Gabe Black
7ef28e9517 cpu: De-templatize the O3 ROB.
Change-Id: I257d2a71be5d4254437d84a5bfa59e2e8dc6420a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42106
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-20 20:08:41 +00:00
Gabe Black
2801cc08c0 cpu: De-templatize the O3 MemDepUnit.
Change-Id: I4c1d6b1246fe4ca9f8a9cc9d434ca20f512f8d2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42105
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-20 20:08:24 +00:00
Gabe Black
4f4df67148 cpu: Remove the MemDepPred template parameter from MemDepUnit.
Hard code this to StoreSet, the only value ever used with this
parameter. If the dependency predictor needs to be updatable, there
should be a well defined interface for it which can be connected at run
time.

Change-Id: Ie30a742eac98220cc39679d26ada5d08099659a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-20 20:08:02 +00:00
Gabe Black
eacc352ebd cpu: Remove comm types from O3CPUImpl.
This struct is now empty, although we still need to keep it until all
the types within O3 have been de-templated and no longer need a template
argument.

Change-Id: I3889bdbb1b8d638f7b04e5bfb7698e35eb7f2e57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42103
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-20 20:07:47 +00:00
Gabe Black
fc51c87329 cpu: Remove the O3CPU type from the O3CPUImpl.
Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42102
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-20 20:07:29 +00:00
Gabe Black
2db8b308e0 cpu: Drop the DynInstPtr types from O3CPUImpl.
Aside from basic code editting, this also moves some methods from the
.hh files to the _impl.hh files. It also changes the Checker CPU
template to take the DynInstPtr type directly instead of through Impl
since that was the only type it used anyway. Finally it sets up a header
file which predeclares the O3DynInstPtr and O3DynInstConstPtr types so
they can be used without having to also include the BaseO3DynInst class
definition to break circular dependencies.

Change-Id: I5ca6af38ec13e6e820abcdb3748412e4f7fc1c78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42101
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-20 20:07:09 +00:00
Gabe Black
ab645bf854 cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.
Change-Id: I0bc160f28f084c8873c3e19be9a4d7a45f9480a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42100
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-20 06:40:58 +00:00
Gabe Black
4abe9ac08b misc: Switch away from the deprecated UNIT_* macros.
Expand the macros in place.

Change-Id: I5dba512b99a1204c23a995e112248b86523b77c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45560
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-19 21:42:34 +00:00
Daniel R. Carvalho
9b675ebea8 misc: Add missing compiler.hh include
Add some missing base/compiler.hh includes.

Found by manually checking the files in:
  grep -r --include \*.hh -L \
    '#include "base/compiler.hh"' \
    $(grep -r -l "GEM5_" src/)

And occasionally checking some .cc files through
a similar methodology.

Change-Id: I6b6e27189c627bb76ace73c338486743d469be46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45459
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-14 10:02:14 +00:00
Gabe Black
02ae343c66 misc: Replace M5_CLASS_VAR_USED with GEM5_CLASS_VAR_USED.
Change-Id: Ibd2230d684f41201b07fa9083881145e36176a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45241
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
fb3befcc6d misc: Replace M5_VAR_USED with GEM5_VAR_USED.
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
f2d3011333 cpu: Get rid of the redundant PhysRegIndex type.
It was defined to be effectively the same type as RegIndex, which is a
uint16_t. Having two types for essentially the same thing (which the
compiler would treat as equivalent) adds unnecessary complexity.

Change-Id: Ibf6badc19e3b0a27c3bc3e68def1e686dbef3ea8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45228
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-05-10 20:04:00 +00:00
Gabe Black
16fa9f9812 arch,cpu: Get rid of is*Reg() methods in RegId.
These bake in the existing set of RegClass values and are not flexible
or scalable.

Change-Id: I107460cd82960d96916d1644403b7635820045a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45226
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-10 20:03:38 +00:00
Gabe Black
41d934cf18 misc: Collapse all uses of DTRACE(x) to Debug::x.
Also mark the DTRACE macro as deprecated.

Change-Id: I99d9a9544b539117b375186e3e425d73d3c5cab7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45009
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-10 20:00:48 +00:00
Gabe Black
d33a693e43 arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
The only thing still in arch/registers.hh were related to vector
registers. To make it obvious that nothing else should be added, this
change renames the file so that it has the much less generic name
arch/vecregs.hh.

Change-Id: I729697dc576e1978047688d9700dc07ff9b17044
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42686
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-07 19:36:08 +00:00
Gabe Black
f1cd6341ea cpu,arch: Move the zero register index into RegClassInfo.
There is a design which has been put forward which eliminates the idea
of a zero register entirely, but in the mean time, to get rid of one
more ISA specific constant, this change moves the ZeroReg constant into
the RegClassInfo class, specifically the IntRegClass instance which is
published by each ISA.

When the idea of zero registers has been eliminated entirely from
non ISA specific code, this and the existing machinery can be
eliminated.

Change-Id: I4302a53220dd5ff6b9b47ecc765bddc6698310ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42685
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 12:48:47 +00:00
Gabe Black
7036e2174f cpu: Pull all remaining non-comm types out of SimpleCPUPolicy.
Change-Id: I79c56533cf6a9d1c982cea3ca9bedc83e6afda49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42099
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-04-29 04:23:25 +00:00
Gabe Black
86059e7a0b cpu: Extract stage classes from O3's SimpleCPUPolicy.
Use the target types directly without that layer of indirection. This
also narrows the scope of some includes.

Change-Id: I152f2ce0684781a9b61bd9d5a38620c39a4c60e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42098
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 04:23:01 +00:00
Gabe Black
729ab6d4d8 cpu: Move MaxWidth and MaxThreads from O3CPUImpl to cpu/o3/limits.hh.
Change-Id: I2534661bbdbd8537129403f97c8fb767a2eb85d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42097
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 03:35:40 +00:00
Gabe Black
3c3c2c3076 cpu: Simplify the RegId class a little.
Having const and non const reference accessors for the RegId index are
basically the same thing as just making the index value public but with
more complexity. Stop allowing updates through the accessor, and
simplify/fix the one location that was using that.

Also, there is no good reason to return an integer value by const
reference instead of returning it by value, since the value being passed
around (a pointer) is the same size, and just makes the value harder to
access.

Change-Id: I377ffc5878ef9bffa2ac53626a87c019a585ab1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42684
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 15:12:42 +00:00
Gabe Black
6f3c197742 cpu: Eliminate the isZeroReg() helper in RegId.
The isZeroReg() helper checked if the register was both an integer
register, and if it equaled TheISA::ZeroReg. This bakes in both the
assumption that any zero registers are integer (and that integer
registers are a thing), and also internalizes the plumbing which selects
what index is the zero register.

This change eliminates the isZeroReg helper and moves the logic inside
it into where it was called. In most cases, it was actually not
necessary to check if the register was integer since that was already
implied by context. This also brings the TheISA::ZeroReg constant out,
where it can be replaced by values plumbed in more generally than a
fixed, ISA specific constant.

Change-Id: I651762b6eb01fea83ec0b0076e8be9bf24b5b0da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42683
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 12:50:48 +00:00
Gabe Black
2d95f59ece arch,cpu: Separate printing and serialization of VecPredReg.
This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
14f14f9a62 arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.

Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 22:39:37 +00:00
Gabe Black
3bd72b42d0 cpu: De-templatize the BaseO3DynInst.
Change-Id: If77561b811e10adf54a8b9e28f61e143ed3ead33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42096
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 08:39:49 +00:00
Gabe Black
f484341215 cpu: Get rid of the unused eaSrcsReady method.
This method wasn't used by anything, and also made very unsafe
assumptions about what different source registers were used for.

Change-Id: I8f58aa70e139d3895499e04c86d8de2530e17d5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42095
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:41 +00:00
Gabe Black
1daf4bf39d cpu: Merge the BaseDynInst and the BaseO3DynInst classes.
Despite the generic sounding name and sort of generic contents, the
BaseDynInst was actually tied to the O3 CPU. Having the two independent
moving pieces created complexity but provided no real benefit. This was
evidenced by the fact that no CPU other than O3 actually used that
class.

Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:13 +00:00
handsomeliu
490b41eaac cpu: Increased the upper bound of cpu issue width
The upper bound was 8, but issue width increased to 12 since Cortex A77.
(https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a77)
This CL increased the upper bound to 12.

Bug: 175759373
Test: gem5/main/config/example/se.py
Change-Id: I9d084b940628a2bcfa676d386d3d1a82ba9b03f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44225
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 07:55:54 +00:00
Daniel R. Carvalho
e7e03df9a9 cpu-o3: Fix missing overrides
Fix missing overrides in SimpleTrace.

Change-Id: I82ed2a10c98ea67dde7b99db13c0ad5d9ed96f0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44405
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 00:09:06 +00:00
Gabe Black
0dade68dae arch,cpu,gpu-compute: Further simplify VecRegContainer.
Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-10 07:31:23 +00:00
Daniel R. Carvalho
5c8983fc18 misc: Fix remaining opening braces
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 01:29:31 +00:00
Daniel R. Carvalho
7f1de4e686 misc: Fix coding style for enum's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 16:26:04 +00:00
Gabe Black
08913caec2 arch,cpu,kern,sim: Eliminate the utility.hh switching header.
This header is no longer used. Remove the places where it's included,
and stop generating it. Also eliminate the now empty SPARC and Power
versions of the header.

Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:58 +00:00
Gabe Black
5ffd619d38 arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:33 +00:00
Gabe Black
2cb09e4042 arch,cpu: Collapse away TheISA::advancePC.
In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
2021-03-22 21:01:07 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Gabe Black
1c35c00c4f arch,cpu: Get rid of the RenameMode template class.
There is no way to make this sort of template work with more than one
ISA at a time, and it's also more complex than it needs to be,
particularly since the methods within it are never used in performance
critical code. Using virtual functions is also simpler and uses less
code.

Change-Id: I0baa1a651fa656420f6f90776572f8700a6d7cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40106
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 00:56:21 +00:00
Gabe Black
e1f2608141 cpu: Fix transitive includes in the O3 rename map and debug faults.
Change-Id: I22f80c24c3128e91fd039b8e3b689d7065440ad0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42964
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 03:51:07 +00:00
Gabe Black
49082c971f arch,cpu: Create register class descriptors.
These currently only hold the number of registers in a particular class,
but can be extended in the future to hold other information about each
class. The ISA class holds a vector of descriptors which other parts of
gem5 can retrieve to set up storage for each class, etc.

Currently, the RegClass enum is used to explicitly index into the vector
of descriptors to get information about a particular class. Once enough
information is stored in the descriptors, the other parts of gem5 should
be able to set up for each register class generically, and the ISAs will
be able to leave out or create new register classes without having to
set up global plumbing for it.

The more immediate benefit is that this should (mostly) parameterize
away the ISA register constants to break another TheISA style
dependency. Currently a global set of descriptors are set up in the
BaseISA class using the old TheISA constants, but it should be easy to
break those out and make the ISAs set up their own descriptors. That
will bring arch/registers.hh significantly closer to being eliminated.

Change-Id: I6d6d1256288f880391246b71045482a4a03c4198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41733
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 04:33:25 +00:00