cpu: De-templatize the O3 InstructionQueue.

Change-Id: Id897b66b4041a6be4c85019585b205e8d8b366e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42108
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>

src/cpu/o3/iew.hh

@@ -351,7 +351,7 @@ class DefaultIEW
 
   public:
     /** Instruction queue. */
-    InstructionQueue<Impl> instQueue;
+    InstructionQueue instQueue;
 
     /** Load / store queue. */
     LSQ<Impl> ldstQueue;

src/cpu/o3/inst_queue.hh

@@ -53,6 +53,7 @@
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dep_graph.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
+#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/mem_dep_unit.hh"
 #include "cpu/o3/store_set.hh"
@@ -88,7 +89,6 @@ class FullO3CPU;
  * have the execute() function called on it.
  * @todo: Make IQ able to handle multiple FU pools.
  */
-template <class Impl>
 class InstructionQueue
 {
   public:
@@ -106,7 +106,7 @@ class InstructionQueue
         int fuIdx;
 
         /** Pointer back to the instruction queue. */
-        InstructionQueue<Impl> *iqPtr;
+        InstructionQueue *iqPtr;
 
         /** Should the FU be added to the list to be freed upon
          * completing this event.
@@ -116,7 +116,7 @@ class InstructionQueue
       public:
         /** Construct a FU completion event. */
         FUCompletion(const O3DynInstPtr &_inst, int fu_idx,
-                     InstructionQueue<Impl> *iq_ptr);
+                     InstructionQueue *iq_ptr);
 
         virtual void process();
         virtual const char *description() const;
@@ -124,8 +124,8 @@ class InstructionQueue
     };
 
     /** Constructs an IQ. */
-    InstructionQueue(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
-                     const DerivO3CPUParams &params);
+    InstructionQueue(FullO3CPU<O3CPUImpl> *cpu_ptr,
+            DefaultIEW<O3CPUImpl> *iew_ptr, const DerivO3CPUParams &params);
 
     /** Destructs the IQ. */
     ~InstructionQueue();
@@ -281,13 +281,13 @@ class InstructionQueue
     /////////////////////////
 
     /** Pointer to the CPU. */
-    FullO3CPU<Impl> *cpu;
+    FullO3CPU<O3CPUImpl> *cpu;
 
     /** Cache interface. */
     MemInterface *dcacheInterface;
 
     /** Pointer to IEW stage. */
-    DefaultIEW<Impl> *iewStage;
+    DefaultIEW<O3CPUImpl> *iewStage;
 
     /** The memory dependence unit, which tracks/predicts memory dependences
      *  between instructions.
@@ -478,7 +478,7 @@ class InstructionQueue
 
     struct IQStats : public Stats::Group
     {
-        IQStats(FullO3CPU<Impl> *cpu, const unsigned &total_width);
+        IQStats(FullO3CPU<O3CPUImpl> *cpu, const unsigned &total_width);
         /** Stat for number of instructions added. */
         Stats::Scalar instsAdded;
         /** Stat for number of non-speculative instructions added. */

src/cpu/o3/lsq_unit.cc

@@ -1028,6 +1028,13 @@ LSQUnit::squash(const InstSeqNum &squashed_num)
     }
 }
 
+uint64_t
+LSQUnit::getLatestHtmUid() const
+{
+    const auto& htm_cpt = cpu->tcBase(lsqID)->getHtmCheckpointPtr();
+    return htm_cpt->getHtmUid();
+}
+
 void
 LSQUnit::storePostSend()
 {
@@ -1257,6 +1264,10 @@ LSQUnit::dumpInsts() const
     cprintf("\n");
 }
 
+void LSQUnit::schedule(Event& ev, Tick when) { cpu->schedule(ev, when); }
+
+BaseMMU *LSQUnit::getMMUPtr() { return cpu->mmu; }
+
 unsigned int
 LSQUnit::cacheLineSize()
 {

src/cpu/o3/lsq_unit.hh

@@ -312,12 +312,9 @@ class LSQUnit
     int numHtmStarts() const { return htmStarts; }
     int numHtmStops() const { return htmStops; }
     void resetHtmStartsStops() { htmStarts = htmStops = 0; }
-    uint64_t getLatestHtmUid() const
-    {
-        const auto& htm_cpt = cpu->tcBase(lsqID)->getHtmCheckpointPtr();
-        return htm_cpt->getHtmUid();
-    }
-    void setLastRetiredHtmUid(uint64_t htm_uid)
+    uint64_t getLatestHtmUid() const;
+    void
+    setLastRetiredHtmUid(uint64_t htm_uid)
     {
         assert(htm_uid >= lastRetiredHtmUid);
         lastRetiredHtmUid = htm_uid;
@@ -393,9 +390,9 @@ class LSQUnit
     void dumpInsts() const;
 
     /** Schedule event for the cpu. */
-    void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); }
+    void schedule(Event& ev, Tick when);
 
-    BaseMMU* getMMUPtr() { return cpu->mmu; }
+    BaseMMU *getMMUPtr();
 
   private:
     /** Pointer to the CPU. */

src/cpu/o3/mem_dep_unit.cc

@@ -144,7 +144,7 @@ MemDepUnit::takeOverFrom()
 }
 
 void
-MemDepUnit::setIQ(InstructionQueue<O3CPUImpl> *iq_ptr)
+MemDepUnit::setIQ(InstructionQueue *iq_ptr)
 {
     iqPtr = iq_ptr;
 }

src/cpu/o3/mem_dep_unit.hh

@@ -68,7 +68,6 @@ struct SNHash
 
 struct DerivO3CPUParams;
 
-template <class Impl>
 class InstructionQueue;
 
 template <class Impl>
@@ -117,7 +116,7 @@ class MemDepUnit
     void takeOverFrom();
 
     /** Sets the pointer to the IQ. */
-    void setIQ(InstructionQueue<O3CPUImpl> *iq_ptr);
+    void setIQ(InstructionQueue *iq_ptr);
 
     /** Inserts a memory instruction. */
     void insert(const O3DynInstPtr &inst);
@@ -258,7 +257,7 @@ class MemDepUnit
     void insertBarrierSN(const O3DynInstPtr &barr_inst);
 
     /** Pointer to the IQ. */
-    InstructionQueue<O3CPUImpl> *iqPtr;
+    InstructionQueue *iqPtr;
 
     /** The thread id of this memory dependence unit. */
     int id;