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cpu: Remove the O3CPU type from the O3CPUImpl.

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Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42102
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-03-03 00:49:08 -08:00
parent 2db8b308e0
commit fc51c87329
26 changed files with 81 additions and 100 deletions
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7
src/cpu/o3/commit.hh
View File

@@ -87,7 +87,6 @@ class DefaultCommit
{
public:
// Typedefs from the Impl.
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::TimeStruct TimeStruct;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::IEWStruct IEWStruct;
@@ -136,7 +135,7 @@ class DefaultCommit
public:
/** Construct a DefaultCommit with the given parameters. */
DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams &params);
DefaultCommit(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
/** Returns the name of the DefaultCommit. */
std::string name() const;
@@ -357,7 +356,7 @@ class DefaultCommit
private:
/** Pointer to O3CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Vector of all of the threads. */
std::vector<Thread *> thread;
@@ -480,7 +479,7 @@ class DefaultCommit
struct CommitStats : public Stats::Group
{
CommitStats(O3CPU *cpu, DefaultCommit *commit);
CommitStats(FullO3CPU<Impl> *cpu, DefaultCommit *commit);
/** Stat for the total number of squashed instructions discarded by
* commit.
*/

11
src/cpu/o3/commit_impl.hh
View File

@@ -79,7 +79,8 @@ DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
}
template <class Impl>
DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams &params)
DefaultCommit<Impl>::DefaultCommit(FullO3CPU<Impl> *_cpu,
const DerivO3CPUParams &params)
: commitPolicy(params.smtCommitPolicy),
cpu(_cpu),
iewToCommitDelay(params.iewToCommitDelay),
@@ -150,7 +151,7 @@ DefaultCommit<Impl>::regProbePoints()
}
template <class Impl>
DefaultCommit<Impl>::CommitStats::CommitStats(O3CPU *cpu,
DefaultCommit<Impl>::CommitStats::CommitStats(FullO3CPU<Impl> *cpu,
DefaultCommit *commit)
: Stats::Group(cpu, "commit"),
ADD_STAT(commitSquashedInsts, Stats::Units::Count::get(),
@@ -344,7 +345,7 @@ DefaultCommit<Impl>::startupStage()
// Commit must broadcast the number of free entries it has at the
// start of the simulation, so it starts as active.
cpu->activateStage(O3CPU::CommitIdx);
cpu->activateStage(FullO3CPU<Impl>::CommitIdx);
cpu->activityThisCycle();
}
@@ -496,10 +497,10 @@ DefaultCommit<Impl>::updateStatus()
if (_nextStatus == Inactive && _status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::CommitIdx);
cpu->deactivateStage(FullO3CPU<Impl>::CommitIdx);
} else if (_nextStatus == Active && _status == Inactive) {
DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(O3CPU::CommitIdx);
cpu->activateStage(FullO3CPU<Impl>::CommitIdx);
}
_status = _nextStatus;

11
src/cpu/o3/cpu.cc
View File

@@ -315,7 +315,7 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
DPRINTF(O3CPU, "Workload[%i] process is %#x",
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
(FullO3CPU *)(this),
tid, params.workload[tid]);
//usedTids[tid] = true;
@@ -326,8 +326,7 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
Process* dummy_proc = NULL;
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, dummy_proc);
this, tid, dummy_proc);
//usedTids[tid] = false;
}
}
@@ -346,8 +345,7 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
o3_tc, this->checker);
}
o3_tc->cpu = (typename Impl::O3CPU *)(this);
assert(o3_tc->cpu);
o3_tc->cpu = this;
o3_tc->thread = this->thread[tid];
// Give the thread the TC.
@@ -391,8 +389,7 @@ FullO3CPU<Impl>::regProbePoints()
}
template <class Impl>
FullO3CPU<Impl>::
FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
FullO3CPU<Impl>::FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
: Stats::Group(cpu),
ADD_STAT(timesIdled, Stats::Units::Count::get(),
"Number of times that the entire CPU went into an idle state "

2
src/cpu/o3/cpu.hh
View File

@@ -101,8 +101,6 @@ class FullO3CPU : public BaseO3CPU
{
public:
// Typedefs from the Impl here.
typedef typename Impl::O3CPU O3CPU;
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;

10
src/cpu/o3/decode.hh
View File

@@ -50,6 +50,9 @@
struct DerivO3CPUParams;
template <class Impl>
class FullO3CPU;
/**
* DefaultDecode class handles both single threaded and SMT
* decode. Its width is specified by the parameters; each cycles it
@@ -62,7 +65,6 @@ class DefaultDecode
{
private:
// Typedefs from the Impl.
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::DecodeStruct DecodeStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -97,7 +99,7 @@ class DefaultDecode
public:
/** DefaultDecode constructor. */
DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams &params);
DefaultDecode(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
void startupStage();
@@ -204,7 +206,7 @@ class DefaultDecode
private:
// Interfaces to objects outside of decode.
/** CPU interface. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
@@ -295,7 +297,7 @@ class DefaultDecode
struct DecodeStats : public Stats::Group
{
DecodeStats(O3CPU *cpu);
DecodeStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of idle cycles. */
Stats::Scalar idleCycles;

9
src/cpu/o3/decode_impl.hh
View File

@@ -59,7 +59,8 @@
using std::list;
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams &params)
DefaultDecode<Impl>::DefaultDecode(FullO3CPU<Impl> *_cpu,
const DerivO3CPUParams &params)
: cpu(_cpu),
renameToDecodeDelay(params.renameToDecodeDelay),
iewToDecodeDelay(params.iewToDecodeDelay),
@@ -122,7 +123,7 @@ DefaultDecode<Impl>::name() const
}
template <class Impl>
DefaultDecode<Impl>::DecodeStats::DecodeStats(O3CPU *cpu)
DefaultDecode<Impl>::DecodeStats::DecodeStats(FullO3CPU<Impl> *cpu)
: Stats::Group(cpu, "decode"),
ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
"Number of cycles decode is idle"),
@@ -457,7 +458,7 @@ DefaultDecode<Impl>::updateStatus()
DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(O3CPU::DecodeIdx);
cpu->activateStage(FullO3CPU<Impl>::DecodeIdx);
}
} else {
// If it's not unblocking, then decode will not have any internal
@@ -466,7 +467,7 @@ DefaultDecode<Impl>::updateStatus()
_status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::DecodeIdx);
cpu->deactivateStage(FullO3CPU<Impl>::DecodeIdx);
}
}
}

7
src/cpu/o3/fetch.hh
View File

@@ -73,7 +73,6 @@ class DefaultFetch
{
public:
/** Typedefs from Impl. */
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::FetchStruct FetchStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -212,7 +211,7 @@ class DefaultFetch
public:
/** DefaultFetch constructor. */
DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams &params);
DefaultFetch(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
/** Returns the name of fetch. */
std::string name() const;
@@ -402,7 +401,7 @@ class DefaultFetch
private:
/** Pointer to the O3CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
@@ -544,7 +543,7 @@ class DefaultFetch
protected:
struct FetchStatGroup : public Stats::Group
{
FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch);
FetchStatGroup(FullO3CPU<Impl> *cpu, DefaultFetch *fetch);
// @todo: Consider making these
// vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */

13
src/cpu/o3/fetch_impl.hh
View File

@@ -73,7 +73,8 @@
#include "sim/system.hh"
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams &params)
DefaultFetch<Impl>::DefaultFetch(FullO3CPU<Impl> *_cpu,
const DerivO3CPUParams &params)
: fetchPolicy(params.smtFetchPolicy),
cpu(_cpu),
branchPred(nullptr),
@@ -158,7 +159,7 @@ DefaultFetch<Impl>::regProbePoints()
template <class Impl>
DefaultFetch<Impl>::
FetchStatGroup::FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch)
FetchStatGroup::FetchStatGroup(FullO3CPU<Impl> *cpu, DefaultFetch *fetch)
: Stats::Group(cpu, "fetch"),
ADD_STAT(icacheStallCycles, Stats::Units::Cycle::get(),
"Number of cycles fetch is stalled on an Icache miss"),
@@ -493,7 +494,7 @@ DefaultFetch<Impl>::switchToActive()
if (_status == Inactive) {
DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(O3CPU::FetchIdx);
cpu->activateStage(FullO3CPU<Impl>::FetchIdx);
_status = Active;
}
@@ -506,7 +507,7 @@ DefaultFetch<Impl>::switchToInactive()
if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::FetchIdx);
cpu->deactivateStage(FullO3CPU<Impl>::FetchIdx);
_status = Inactive;
}
@@ -831,7 +832,7 @@ DefaultFetch<Impl>::updateFetchStatus()
"completion\n",tid);
}
cpu->activateStage(O3CPU::FetchIdx);
cpu->activateStage(FullO3CPU<Impl>::FetchIdx);
}
return Active;
@@ -842,7 +843,7 @@ DefaultFetch<Impl>::updateFetchStatus()
if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::FetchIdx);
cpu->deactivateStage(FullO3CPU<Impl>::FetchIdx);
}
return Inactive;

9
src/cpu/o3/iew.hh
View File

@@ -82,7 +82,6 @@ class DefaultIEW
{
private:
//Typedefs from Impl
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::TimeStruct TimeStruct;
typedef typename Impl::IEWStruct IEWStruct;
typedef typename Impl::RenameStruct RenameStruct;
@@ -129,7 +128,7 @@ class DefaultIEW
public:
/** Constructs a DefaultIEW with the given parameters. */
DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams &params);
DefaultIEW(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
/** Returns the name of the DefaultIEW stage. */
std::string name() const;
@@ -347,7 +346,7 @@ class DefaultIEW
private:
/** CPU pointer. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Records if IEW has written to the time buffer this cycle, so that the
* CPU can deschedule itself if there is no activity.
@@ -424,7 +423,7 @@ class DefaultIEW
struct IEWStats : public Stats::Group
{
IEWStats(O3CPU *cpu);
IEWStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of idle cycles. */
Stats::Scalar idleCycles;
@@ -460,7 +459,7 @@ class DefaultIEW
struct ExecutedInstStats : public Stats::Group
{
ExecutedInstStats(O3CPU* cpu);
ExecutedInstStats(FullO3CPU<Impl> *cpu);
/** Stat for total number of executed instructions. */
Stats::Scalar numInsts;

16
src/cpu/o3/iew_impl.hh
View File

@@ -62,7 +62,8 @@
#include "params/DerivO3CPU.hh"
template<class Impl>
DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams &params)
DefaultIEW<Impl>::DefaultIEW(FullO3CPU<Impl> *_cpu,
const DerivO3CPUParams &params)
: issueToExecQueue(params.backComSize, params.forwardComSize),
cpu(_cpu),
instQueue(_cpu, this, params),
@@ -142,8 +143,7 @@ DefaultIEW<Impl>::regProbePoints()
}
template <class Impl>
DefaultIEW<Impl>::
IEWStats::IEWStats(O3CPU *cpu)
DefaultIEW<Impl>::IEWStats::IEWStats(FullO3CPU<Impl> *cpu)
: Stats::Group(cpu),
ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
"Number of cycles IEW is idle"),
@@ -218,8 +218,8 @@ IEWStats::IEWStats(O3CPU *cpu)
}
template <class Impl>
DefaultIEW<Impl>::IEWStats::
ExecutedInstStats::ExecutedInstStats(O3CPU *cpu)
DefaultIEW<Impl>::IEWStats::ExecutedInstStats::ExecutedInstStats(
FullO3CPU<Impl> *cpu)
: Stats::Group(cpu),
ADD_STAT(numInsts, Stats::Units::Count::get(),
"Number of executed instructions"),
@@ -288,7 +288,7 @@ DefaultIEW<Impl>::startupStage()
cpu->checker->setDcachePort(&ldstQueue.getDataPort());
}
cpu->activateStage(O3CPU::IEWIdx);
cpu->activateStage(FullO3CPU<Impl>::IEWIdx);
}
template<class Impl>
@@ -865,7 +865,7 @@ inline void
DefaultIEW<Impl>::activateStage()
{
DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(O3CPU::IEWIdx);
cpu->activateStage(FullO3CPU<Impl>::IEWIdx);
}
template <class Impl>
@@ -873,7 +873,7 @@ inline void
DefaultIEW<Impl>::deactivateStage()
{
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::IEWIdx);
cpu->deactivateStage(FullO3CPU<Impl>::IEWIdx);
}
template<class Impl>

14
src/cpu/o3/impl.hh
View File

@@ -31,10 +31,6 @@
#include "cpu/o3/comm.hh"
// Forward declarations.
template <class Impl>
class FullO3CPU;
/** Implementation specific struct that defines several key types to the
* CPU, the stages within the CPU, the time buffers, and the DynInst.
* The struct defines the ISA, the CPU policy, the specific DynInst, the
@@ -62,16 +58,6 @@ struct O3CPUImpl
/** The struct for all backwards communication. */
typedef TimeBufStruct<O3CPUImpl> TimeStruct;
/** The O3CPU type to be used. */
typedef FullO3CPU<O3CPUImpl> O3CPU;
/** Same typedef, but for CPUType. BaseDynInst may not always use
* an O3 CPU, so it's clearer to call it CPUType instead in that
* case.
*/
typedef O3CPU CPUType;
};
#endif // __CPU_O3_SPARC_IMPL_HH__

10
src/cpu/o3/inst_queue.hh
View File

@@ -67,6 +67,9 @@ class MemInterface;
template <class Impl>
class DefaultIEW;
template <class Impl>
class FullO3CPU;
/**
* A standard instruction queue class. It holds ready instructions, in
* order, in seperate priority queues to facilitate the scheduling of
@@ -89,7 +92,6 @@ class InstructionQueue
{
public:
//Typedefs from the Impl.
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::IssueStruct IssueStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -125,7 +127,7 @@ class InstructionQueue
};
/** Constructs an IQ. */
InstructionQueue(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
InstructionQueue(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams &params);
/** Destructs the IQ. */
@@ -282,7 +284,7 @@ class InstructionQueue
/////////////////////////
/** Pointer to the CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Cache interface. */
MemInterface *dcacheInterface;
@@ -479,7 +481,7 @@ class InstructionQueue
struct IQStats : public Stats::Group
{
IQStats(O3CPU *cpu, const unsigned &total_width);
IQStats(FullO3CPU<Impl> *cpu, const unsigned &total_width);
/** Stat for number of instructions added. */
Stats::Scalar instsAdded;
/** Stat for number of non-speculative instructions added. */

4
src/cpu/o3/inst_queue_impl.hh
View File

@@ -84,7 +84,7 @@ InstructionQueue<Impl>::FUCompletion::description() const
}
template <class Impl>
InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr,
InstructionQueue<Impl>::InstructionQueue(FullO3CPU<Impl> *cpu_ptr,
DefaultIEW<Impl> *iew_ptr, const DerivO3CPUParams &params)
: cpu(cpu_ptr),
iewStage(iew_ptr),
@@ -177,7 +177,7 @@ InstructionQueue<Impl>::name() const
template <class Impl>
InstructionQueue<Impl>::
IQStats::IQStats(O3CPU *cpu, const unsigned &total_width)
IQStats::IQStats(FullO3CPU<Impl> *cpu, const unsigned &total_width)
: Stats::Group(cpu),
ADD_STAT(instsAdded, Stats::Units::Count::get(),
"Number of instructions added to the IQ (excludes non-spec)"),

6
src/cpu/o3/lsq.hh
View File

@@ -75,8 +75,6 @@ template <class Impl>
class LSQ
{
public:
typedef typename Impl::O3CPU O3CPU;
class LSQRequest;
/** Derived class to hold any sender state the LSQ needs. */
class LSQSenderState : public Packet::SenderState
@@ -794,7 +792,7 @@ class LSQ
};
/** Constructs an LSQ with the given parameters. */
LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
LSQ(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams &params);
~LSQ() { }
@@ -1051,7 +1049,7 @@ class LSQ
const std::vector<bool>& byte_enable);
/** The CPU pointer. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** The IEW stage pointer. */
DefaultIEW<Impl> *iewStage;

2
src/cpu/o3/lsq_impl.hh
View File

@@ -68,7 +68,7 @@ LSQ<Impl>::LSQSenderState::contextId()
}
template <class Impl>
LSQ<Impl>::LSQ(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
LSQ<Impl>::LSQ(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams &params)
: cpu(cpu_ptr), iewStage(iew_ptr),
_cacheBlocked(false),

5
src/cpu/o3/lsq_unit.hh
View File

@@ -85,7 +85,6 @@ class LSQUnit
public:
static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::IssueStruct IssueStruct;
using LSQSenderState = typename LSQ<Impl>::LSQSenderState;
@@ -225,7 +224,7 @@ class LSQUnit
}
/** Initializes the LSQ unit with the specified number of entries. */
void init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
void init(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams &params, LSQ<Impl> *lsq_ptr, unsigned id);
/** Returns the name of the LSQ unit. */
@@ -398,7 +397,7 @@ class LSQUnit
private:
/** Pointer to the CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Pointer to the IEW stage. */
DefaultIEW<Impl> *iewStage;

2
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -215,7 +215,7 @@ LSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
template<class Impl>
void
LSQUnit<Impl>::init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
LSQUnit<Impl>::init(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
const DerivO3CPUParams &params, LSQ<Impl> *lsq_ptr, unsigned id)
{
lsqID = id;

8
src/cpu/o3/mem_dep_unit.hh
View File

@@ -68,6 +68,9 @@ struct DerivO3CPUParams;
template <class Impl>
class InstructionQueue;
template <class Impl>
class FullO3CPU;
/**
* Memory dependency unit class. This holds the memory dependence predictor.
* As memory operations are issued to the IQ, they are also issued to this
@@ -86,8 +89,6 @@ class MemDepUnit
std::string _name;
public:
typedef typename Impl::O3CPU O3CPU;
/** Empty constructor. Must call init() prior to using in this case. */
MemDepUnit();
@@ -101,7 +102,8 @@ class MemDepUnit
std::string name() const { return _name; }
/** Initializes the unit with parameters and a thread id. */
void init(const DerivO3CPUParams &params, ThreadID tid, O3CPU *cpu);
void init(const DerivO3CPUParams &params, ThreadID tid,
FullO3CPU<Impl> *cpu);
/** Determine if we are drained. */
bool isDrained() const;

2
src/cpu/o3/mem_dep_unit_impl.hh
View File

@@ -99,7 +99,7 @@ MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::init(
const DerivO3CPUParams &params, ThreadID tid, O3CPU *cpu)
const DerivO3CPUParams &params, ThreadID tid, FullO3CPU<Impl> *cpu)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);

3
src/cpu/o3/probe/elastic_trace.hh
View File

@@ -60,6 +60,9 @@
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
template <class Impl>
class FullO3CPU;
/**
* The elastic trace is a type of probe listener and listens to probe points
* in multiple stages of the O3CPU. The notify method is called on a probe

5
src/cpu/o3/rename.hh
View File

@@ -74,7 +74,6 @@ class DefaultRename
{
public:
// Typedefs from the Impl.
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DecodeStruct DecodeStruct;
typedef typename Impl::RenameStruct RenameStruct;
typedef typename Impl::TimeStruct TimeStruct;
@@ -126,7 +125,7 @@ class DefaultRename
public:
/** DefaultRename constructor. */
DefaultRename(O3CPU *_cpu, const DerivO3CPUParams &params);
DefaultRename(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
/** Returns the name of rename. */
std::string name() const;
@@ -320,7 +319,7 @@ class DefaultRename
std::list<RenameHistory> historyBuffer[O3MaxThreads];
/** Pointer to CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Pointer to main time buffer used for backwards communication. */
TimeBuffer<TimeStruct> *timeBuffer;

7
src/cpu/o3/rename_impl.hh
View File

@@ -53,7 +53,8 @@
#include "params/DerivO3CPU.hh"
template <class Impl>
DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, const DerivO3CPUParams &params)
DefaultRename<Impl>::DefaultRename(FullO3CPU<Impl> *_cpu,
const DerivO3CPUParams &params)
: cpu(_cpu),
iewToRenameDelay(params.iewToRenameDelay),
decodeToRenameDelay(params.decodeToRenameDelay),
@@ -865,7 +866,7 @@ DefaultRename<Impl>::updateStatus()
DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(O3CPU::RenameIdx);
cpu->activateStage(FullO3CPU<Impl>::RenameIdx);
}
} else {
// If it's not unblocking, then rename will not have any internal
@@ -874,7 +875,7 @@ DefaultRename<Impl>::updateStatus()
_status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(O3CPU::RenameIdx);
cpu->deactivateStage(FullO3CPU<Impl>::RenameIdx);
}
}
}

7
src/cpu/o3/rob.hh
View File

@@ -58,9 +58,6 @@ template <class Impl>
class ROB
{
public:
//Typedefs from the Impl.
typedef typename Impl::O3CPU O3CPU;
typedef std::pair<RegIndex, RegIndex> UnmapInfo;
typedef typename std::list<O3DynInstPtr>::iterator InstIt;
@@ -84,7 +81,7 @@ class ROB
* @param _cpu The cpu object pointer.
* @param params The cpu params including several ROB-specific parameters.
*/
ROB(O3CPU *_cpu, const DerivO3CPUParams &params);
ROB(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params);
std::string name() const;
@@ -261,7 +258,7 @@ class ROB
void resetState();
/** Pointer to the CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
/** Active Threads in CPU */
std::list<ThreadID> *activeThreads;

2
src/cpu/o3/rob_impl.hh
View File

@@ -51,7 +51,7 @@
#include "params/DerivO3CPU.hh"
template <class Impl>
ROB<Impl>::ROB(O3CPU *_cpu, const DerivO3CPUParams &params)
ROB<Impl>::ROB(FullO3CPU<Impl> *_cpu, const DerivO3CPUParams &params)
: robPolicy(params.smtROBPolicy),
cpu(_cpu),
numEntries(params.numROBEntries),

4
src/cpu/o3/thread_context.hh
View File

@@ -63,10 +63,8 @@ template <class Impl>
class O3ThreadContext : public ThreadContext
{
public:
typedef typename Impl::O3CPU O3CPU;
/** Pointer to the CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
bool
schedule(PCEvent *e) override

5
src/cpu/o3/thread_state.hh
View File

@@ -64,11 +64,10 @@ template <class Impl>
struct O3ThreadState : public ThreadState
{
typedef ThreadContext::Status Status;
typedef typename Impl::O3CPU O3CPU;
private:
/** Pointer to the CPU. */
O3CPU *cpu;
FullO3CPU<Impl> *cpu;
public:
PCEventQueue pcEventQueue;
@@ -96,7 +95,7 @@ struct O3ThreadState : public ThreadState
/** Pointer to the hardware transactional memory checkpoint. */
std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
O3ThreadState(FullO3CPU<Impl> *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, _thread_num, _process), cpu(_cpu),
comInstEventQueue("instruction-based event queue"),
noSquashFromTC(false), trapPending(false), tc(nullptr)