cpu: De-templatize the FullO3CPU class.

Change-Id: Ib7f1e40447a2f5a49e0c9a3af8579d075d5d3625 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42117 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com> Maintainer: Gabe Black <gabe.black@gmail.com>
2021-03-03 05:00:33 -08:00
parent 4ba06c8f25
commit fda2e46a9e
29 changed files with 210 additions and 337 deletions
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -52,6 +52,7 @@
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/o3/cpu.hh"
 #include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/thread_state.hh"
@@ -75,8 +76,7 @@ DefaultCommit::processTrapEvent(ThreadID tid)
    trapSquash[tid] = true;
 }

-DefaultCommit::DefaultCommit(FullO3CPU<O3CPUImpl> *_cpu,
-        const DerivO3CPUParams &params)
+DefaultCommit::DefaultCommit(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : commitPolicy(params.smtCommitPolicy),
      cpu(_cpu),
      iewToCommitDelay(params.iewToCommitDelay),
@@ -144,8 +144,7 @@ DefaultCommit::regProbePoints()
            cpu->getProbeManager(), "Squash");
 }

-DefaultCommit::CommitStats::CommitStats(FullO3CPU<O3CPUImpl> *cpu,
-        DefaultCommit *commit)
+DefaultCommit::CommitStats::CommitStats(FullO3CPU *cpu, DefaultCommit *commit)
    : Stats::Group(cpu, "commit"),
      ADD_STAT(commitSquashedInsts, Stats::Units::Count::get(),
               "The number of squashed insts skipped by commit"),
@@ -328,7 +327,7 @@ DefaultCommit::startupStage()

    // Commit must broadcast the number of free entries it has at the
    // start of the simulation, so it starts as active.
-    cpu->activateStage(FullO3CPU<O3CPUImpl>::CommitIdx);
+    cpu->activateStage(FullO3CPU::CommitIdx);

    cpu->activityThisCycle();
 }
@@ -470,10 +469,10 @@ DefaultCommit::updateStatus()

    if (_nextStatus == Inactive && _status == Active) {
        DPRINTF(Activity, "Deactivating stage.\n");
-        cpu->deactivateStage(FullO3CPU<O3CPUImpl>::CommitIdx);
+        cpu->deactivateStage(FullO3CPU::CommitIdx);
    } else if (_nextStatus == Active && _status == Inactive) {
        DPRINTF(Activity, "Activating stage.\n");
-        cpu->activateStage(FullO3CPU<O3CPUImpl>::CommitIdx);
+        cpu->activateStage(FullO3CPU::CommitIdx);
    }

    _status = _nextStatus;
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -129,7 +129,7 @@ class DefaultCommit

  public:
    /** Construct a DefaultCommit with the given parameters. */
-    DefaultCommit(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    DefaultCommit(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    /** Returns the name of the DefaultCommit. */
    std::string name() const;
@@ -350,7 +350,7 @@ class DefaultCommit

  private:
    /** Pointer to O3CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Vector of all of the threads. */
    std::vector<Thread *> thread;
@@ -470,7 +470,7 @@ class DefaultCommit

    struct CommitStats : public Stats::Group
    {
-        CommitStats(FullO3CPU<O3CPUImpl> *cpu, DefaultCommit *commit);
+        CommitStats(FullO3CPU *cpu, DefaultCommit *commit);
        /** Stat for the total number of squashed instructions discarded by
         * commit.
         */
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -64,8 +64,7 @@

 struct BaseCPUParams;

-template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
+FullO3CPU::FullO3CPU(const DerivO3CPUParams &params)
    : BaseCPU(params),
      mmu(params.mmu),
      tickEvent([this]{ tick(); }, "FullO3CPU tick",
@@ -132,7 +131,7 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
    if (params.checker) {
        BaseCPU *temp_checker = params.checker;
        checker = dynamic_cast<Checker<O3DynInstPtr> *>(temp_checker);
-        checker->setIcachePort(&this->fetch.getInstPort());
+        checker->setIcachePort(&fetch.getInstPort());
        checker->setSystem(params.system);
    } else {
        checker = NULL;
@@ -298,20 +297,19 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
    DPRINTF(O3CPU, "Creating O3CPU object.\n");

    // Setup any thread state.
-    this->thread.resize(this->numThreads);
+    thread.resize(numThreads);

-    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
+    for (ThreadID tid = 0; tid < numThreads; ++tid) {
        if (FullSystem) {
            // SMT is not supported in FS mode yet.
-            assert(this->numThreads == 1);
-            this->thread[tid] = new Thread(this, 0, NULL);
+            assert(numThreads == 1);
+            thread[tid] = new O3ThreadState<O3CPUImpl>(this, 0, NULL);
        } else {
            if (tid < params.workload.size()) {
-                DPRINTF(O3CPU, "Workload[%i] process is %#x",
-                        tid, this->thread[tid]);
-                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                        (FullO3CPU *)(this),
-                        tid, params.workload[tid]);
+                DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
+                        thread[tid]);
+                thread[tid] = new O3ThreadState<O3CPUImpl>(this, tid,
+                        params.workload[tid]);

                //usedTids[tid] = true;
                //threadMap[tid] = tid;
@@ -320,8 +318,8 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
                //when scheduling threads to CPU
                Process* dummy_proc = NULL;

-                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                        this, tid, dummy_proc);
+                thread[tid] = new O3ThreadState<O3CPUImpl>(this, tid,
+                        dummy_proc);
                //usedTids[tid] = false;
            }
        }
@@ -336,18 +334,17 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
        // If we're using a checker, then the TC should be the
        // CheckerThreadContext.
        if (params.checker) {
-            tc = new CheckerThreadContext<O3ThreadContext>(
-                    o3_tc, this->checker);
+            tc = new CheckerThreadContext<O3ThreadContext>(o3_tc, checker);
        }

        o3_tc->cpu = this;
-        o3_tc->thread = this->thread[tid];
+        o3_tc->thread = thread[tid];

        // Give the thread the TC.
-        this->thread[tid]->tc = tc;
+        thread[tid]->tc = tc;

        // Add the TC to the CPU's list of TC's.
-        this->threadContexts.push_back(tc);
+        threadContexts.push_back(tc);
    }

    // FullO3CPU always requires an interrupt controller.
@@ -356,18 +353,12 @@ FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams &params)
              "Ensure createInterruptController() is called.\n", name());
    }

-    for (ThreadID tid = 0; tid < this->numThreads; tid++)
-        this->thread[tid]->setFuncExeInst(0);
+    for (ThreadID tid = 0; tid < numThreads; tid++)
+        thread[tid]->setFuncExeInst(0);
 }

-template <class Impl>
-FullO3CPU<Impl>::~FullO3CPU()
-{
-}
-
-template <class Impl>
 void
-FullO3CPU<Impl>::regProbePoints()
+FullO3CPU::regProbePoints()
 {
    BaseCPU::regProbePoints();

@@ -383,8 +374,7 @@ FullO3CPU<Impl>::regProbePoints()
    commit.regProbePoints();
 }

-template <class Impl>
-FullO3CPU<Impl>::FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
+FullO3CPU::FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
    : Stats::Group(cpu),
      ADD_STAT(timesIdled, Stats::Units::Count::get(),
               "Number of times that the entire CPU went into an idle state "
@@ -511,9 +501,8 @@ FullO3CPU<Impl>::FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
        .prereq(miscRegfileWrites);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::tick()
+FullO3CPU::tick()
 {
    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
    assert(!switchedOut());
@@ -570,9 +559,8 @@ FullO3CPU<Impl>::tick()
    tryDrain();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::init()
+FullO3CPU::init()
 {
    BaseCPU::init();

@@ -591,9 +579,8 @@ FullO3CPU<Impl>::init()
    commit.setThreads(thread);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::startup()
+FullO3CPU::startup()
 {
    BaseCPU::startup();

@@ -604,9 +591,8 @@ FullO3CPU<Impl>::startup()
    commit.startupStage();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::activateThread(ThreadID tid)
+FullO3CPU::activateThread(ThreadID tid)
 {
    std::list<ThreadID>::iterator isActive =
        std::find(activeThreads.begin(), activeThreads.end(), tid);
@@ -622,9 +608,8 @@ FullO3CPU<Impl>::activateThread(ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::deactivateThread(ThreadID tid)
+FullO3CPU::deactivateThread(ThreadID tid)
 {
    // hardware transactional memory
    // shouldn't deactivate thread in the middle of a transaction
@@ -647,9 +632,8 @@ FullO3CPU<Impl>::deactivateThread(ThreadID tid)
    commit.deactivateThread(tid);
 }

-template <class Impl>
 Counter
-FullO3CPU<Impl>::totalInsts() const
+FullO3CPU::totalInsts() const
 {
    Counter total(0);

@@ -660,9 +644,8 @@ FullO3CPU<Impl>::totalInsts() const
    return total;
 }

-template <class Impl>
 Counter
-FullO3CPU<Impl>::totalOps() const
+FullO3CPU::totalOps() const
 {
    Counter total(0);

@@ -673,9 +656,8 @@ FullO3CPU<Impl>::totalOps() const
    return total;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::activateContext(ThreadID tid)
+FullO3CPU::activateContext(ThreadID tid)
 {
    assert(!switchedOut());

@@ -712,9 +694,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::suspendContext(ThreadID tid)
+FullO3CPU::suspendContext(ThreadID tid)
 {
    DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
    assert(!switchedOut());
@@ -733,9 +714,8 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
    BaseCPU::suspendContext(tid);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::haltContext(ThreadID tid)
+FullO3CPU::haltContext(ThreadID tid)
 {
    //For now, this is the same as deallocate
    DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
@@ -756,9 +736,8 @@ FullO3CPU<Impl>::haltContext(ThreadID tid)
    updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::insertThread(ThreadID tid)
+FullO3CPU::insertThread(ThreadID tid)
 {
    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
    // Will change now that the PC and thread state is internal to the CPU
@@ -793,7 +772,7 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
    }

    //Copy Thread Data Into RegFile
-    //this->copyFromTC(tid);
+    //copyFromTC(tid);

    //Set PC/NPC/NNPC
    pcState(src_tc->pcState(), tid);
@@ -806,15 +785,14 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
    commit.rob->resetEntries();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::removeThread(ThreadID tid)
+FullO3CPU::removeThread(ThreadID tid)
 {
    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);

    // Copy Thread Data From RegFile
    // If thread is suspended, it might be re-allocated
-    // this->copyToTC(tid);
+    // copyToTC(tid);


    // @todo: 2-27-2008: Fix how we free up rename mappings
@@ -859,9 +837,8 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
 */
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setVectorsAsReady(ThreadID tid)
+FullO3CPU::setVectorsAsReady(ThreadID tid)
 {
    const auto &regClasses = isa[tid]->regClasses();

@@ -883,11 +860,10 @@ FullO3CPU<Impl>::setVectorsAsReady(ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
+FullO3CPU::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
 {
-    auto pc = this->pcState(tid);
+    auto pc = pcState(tid);

    // new_mode is the new vector renaming mode
    auto new_mode = isa[tid]->vecRegRenameMode(thread[tid]->getTC());
@@ -903,17 +879,15 @@ FullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
    }
 }

-template <class Impl>
 Fault
-FullO3CPU<Impl>::getInterrupts()
+FullO3CPU::getInterrupts()
 {
    // Check if there are any outstanding interrupts
-    return this->interrupts[0]->getInterrupt();
+    return interrupts[0]->getInterrupt();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
+FullO3CPU::processInterrupts(const Fault &interrupt)
 {
    // Check for interrupts here.  For now can copy the code that
    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
@@ -922,38 +896,33 @@ FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
    // @todo: Allow other threads to handle interrupts.

    assert(interrupt != NoFault);
-    this->interrupts[0]->updateIntrInfo();
+    interrupts[0]->updateIntrInfo();

    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
-    this->trap(interrupt, 0, nullptr);
+    trap(interrupt, 0, nullptr);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
-                      const StaticInstPtr &inst)
+FullO3CPU::trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
 {
    // Pass the thread's TC into the invoke method.
-    fault->invoke(this->threadContexts[tid], inst);
+    fault->invoke(threadContexts[tid], inst);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
+FullO3CPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
 {
    thread[tid]->serialize(cp);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
+FullO3CPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
 {
    thread[tid]->unserialize(cp);
 }

-template <class Impl>
 DrainState
-FullO3CPU<Impl>::drain()
+FullO3CPU::drain()
 {
    // Deschedule any power gating event (if any)
    deschedulePowerGatingEvent();
@@ -1014,9 +983,8 @@ FullO3CPU<Impl>::drain()
    }
 }

-template <class Impl>
 bool
-FullO3CPU<Impl>::tryDrain()
+FullO3CPU::tryDrain()
 {
    if (drainState() != DrainState::Draining || !isCpuDrained())
        return false;
@@ -1030,9 +998,8 @@ FullO3CPU<Impl>::tryDrain()
    return true;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::drainSanityCheck() const
+FullO3CPU::drainSanityCheck() const
 {
    assert(isCpuDrained());
    fetch.drainSanityCheck();
@@ -1042,9 +1009,8 @@ FullO3CPU<Impl>::drainSanityCheck() const
    commit.drainSanityCheck();
 }

-template <class Impl>
 bool
-FullO3CPU<Impl>::isCpuDrained() const
+FullO3CPU::isCpuDrained() const
 {
    bool drained(true);

@@ -1081,16 +1047,14 @@ FullO3CPU<Impl>::isCpuDrained() const
    return drained;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::commitDrained(ThreadID tid)
+FullO3CPU::commitDrained(ThreadID tid)
 {
    fetch.drainStall(tid);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::drainResume()
+FullO3CPU::drainResume()
 {
    if (switchedOut())
        return;
@@ -1118,9 +1082,8 @@ FullO3CPU<Impl>::drainResume()
    schedulePowerGatingEvent();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::switchOut()
+FullO3CPU::switchOut()
 {
    DPRINTF(O3CPU, "Switching out\n");
    BaseCPU::switchOut();
@@ -1133,9 +1096,8 @@ FullO3CPU<Impl>::switchOut()
        checker->switchOut();
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
+FullO3CPU::takeOverFrom(BaseCPU *oldCPU)
 {
    BaseCPU::takeOverFrom(oldCPU);

@@ -1147,7 +1109,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)

    assert(!tickEvent.scheduled());

-    FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
+    auto *oldO3CPU = dynamic_cast<FullO3CPU *>(oldCPU);
    if (oldO3CPU)
        globalSeqNum = oldO3CPU->globalSeqNum;

@@ -1155,9 +1117,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
    _status = Idle;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::verifyMemoryMode() const
+FullO3CPU::verifyMemoryMode() const
 {
    if (!system->isTimingMode()) {
        fatal("The O3 CPU requires the memory system to be in "
@@ -1165,153 +1126,133 @@ FullO3CPU<Impl>::verifyMemoryMode() const
    }
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
+FullO3CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
-    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
+    return isa[tid]->readMiscRegNoEffect(misc_reg);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
+FullO3CPU::readMiscReg(int misc_reg, ThreadID tid)
 {
    cpuStats.miscRegfileReads++;
-    return this->isa[tid]->readMiscReg(misc_reg);
+    return isa[tid]->readMiscReg(misc_reg);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
+FullO3CPU::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
 {
-    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
+    isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
+FullO3CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
 {
    cpuStats.miscRegfileWrites++;
-    this->isa[tid]->setMiscReg(misc_reg, val);
+    isa[tid]->setMiscReg(misc_reg, val);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
+FullO3CPU::readIntReg(PhysRegIdPtr phys_reg)
 {
    cpuStats.intRegfileReads++;
    return regFile.readIntReg(phys_reg);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
+FullO3CPU::readFloatReg(PhysRegIdPtr phys_reg)
 {
    cpuStats.fpRegfileReads++;
    return regFile.readFloatReg(phys_reg);
 }

-template <class Impl>
 const TheISA::VecRegContainer&
-FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
+FullO3CPU::readVecReg(PhysRegIdPtr phys_reg) const
 {
    cpuStats.vecRegfileReads++;
    return regFile.readVecReg(phys_reg);
 }

-template <class Impl>
 TheISA::VecRegContainer&
-FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
+FullO3CPU::getWritableVecReg(PhysRegIdPtr phys_reg)
 {
    cpuStats.vecRegfileWrites++;
    return regFile.getWritableVecReg(phys_reg);
 }

-template <class Impl>
 const TheISA::VecElem&
-FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const
+FullO3CPU::readVecElem(PhysRegIdPtr phys_reg) const
 {
    cpuStats.vecRegfileReads++;
    return regFile.readVecElem(phys_reg);
 }

-template <class Impl>
 const TheISA::VecPredRegContainer&
-FullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const
+FullO3CPU::readVecPredReg(PhysRegIdPtr phys_reg) const
 {
    cpuStats.vecPredRegfileReads++;
    return regFile.readVecPredReg(phys_reg);
 }

-template <class Impl>
 TheISA::VecPredRegContainer&
-FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
+FullO3CPU::getWritableVecPredReg(PhysRegIdPtr phys_reg)
 {
    cpuStats.vecPredRegfileWrites++;
    return regFile.getWritableVecPredReg(phys_reg);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
+FullO3CPU::readCCReg(PhysRegIdPtr phys_reg)
 {
    cpuStats.ccRegfileReads++;
    return regFile.readCCReg(phys_reg);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
+FullO3CPU::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
 {
    cpuStats.intRegfileWrites++;
    regFile.setIntReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
+FullO3CPU::setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
 {
    cpuStats.fpRegfileWrites++;
    regFile.setFloatReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg,
-        const TheISA::VecRegContainer& val)
+FullO3CPU::setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer& val)
 {
    cpuStats.vecRegfileWrites++;
    regFile.setVecReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem& val)
+FullO3CPU::setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem& val)
 {
    cpuStats.vecRegfileWrites++;
    regFile.setVecElem(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
+FullO3CPU::setVecPredReg(PhysRegIdPtr phys_reg,
                               const TheISA::VecPredRegContainer& val)
 {
    cpuStats.vecPredRegfileWrites++;
    regFile.setVecPredReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
+FullO3CPU::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
 {
    cpuStats.ccRegfileWrites++;
    regFile.setCCReg(phys_reg, val);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
+FullO3CPU::readArchIntReg(int reg_idx, ThreadID tid)
 {
    cpuStats.intRegfileReads++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1320,9 +1261,8 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
    return regFile.readIntReg(phys_reg);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
+FullO3CPU::readArchFloatReg(int reg_idx, ThreadID tid)
 {
    cpuStats.fpRegfileReads++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1331,27 +1271,24 @@ FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
    return regFile.readFloatReg(phys_reg);
 }

-template <class Impl>
 const TheISA::VecRegContainer&
-FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
+FullO3CPU::readArchVecReg(int reg_idx, ThreadID tid) const
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                RegId(VecRegClass, reg_idx));
    return readVecReg(phys_reg);
 }

-template <class Impl>
 TheISA::VecRegContainer&
-FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
+FullO3CPU::getWritableArchVecReg(int reg_idx, ThreadID tid)
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                RegId(VecRegClass, reg_idx));
    return getWritableVecReg(phys_reg);
 }

-template <class Impl>
 const TheISA::VecElem&
-FullO3CPU<Impl>::readArchVecElem(
+FullO3CPU::readArchVecElem(
        const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1359,27 +1296,24 @@ FullO3CPU<Impl>::readArchVecElem(
    return readVecElem(phys_reg);
 }

-template <class Impl>
 const TheISA::VecPredRegContainer&
-FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
+FullO3CPU::readArchVecPredReg(int reg_idx, ThreadID tid) const
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                RegId(VecPredRegClass, reg_idx));
    return readVecPredReg(phys_reg);
 }

-template <class Impl>
 TheISA::VecPredRegContainer&
-FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
+FullO3CPU::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                RegId(VecPredRegClass, reg_idx));
    return getWritableVecPredReg(phys_reg);
 }

-template <class Impl>
 RegVal
-FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
+FullO3CPU::readArchCCReg(int reg_idx, ThreadID tid)
 {
    cpuStats.ccRegfileReads++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1388,9 +1322,8 @@ FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
    return regFile.readCCReg(phys_reg);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
+FullO3CPU::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
 {
    cpuStats.intRegfileWrites++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1399,9 +1332,8 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
    regFile.setIntReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
+FullO3CPU::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
 {
    cpuStats.fpRegfileWrites++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1410,19 +1342,17 @@ FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
    regFile.setFloatReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchVecReg(int reg_idx,
-        const TheISA::VecRegContainer& val, ThreadID tid)
+FullO3CPU::setArchVecReg(int reg_idx, const TheISA::VecRegContainer& val,
+        ThreadID tid)
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                RegId(VecRegClass, reg_idx));
    setVecReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
+FullO3CPU::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                                const TheISA::VecElem& val, ThreadID tid)
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1430,9 +1360,8 @@ FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
    setVecElem(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchVecPredReg(int reg_idx,
+FullO3CPU::setArchVecPredReg(int reg_idx,
        const TheISA::VecPredRegContainer& val, ThreadID tid)
 {
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1440,9 +1369,8 @@ FullO3CPU<Impl>::setArchVecPredReg(int reg_idx,
    setVecPredReg(phys_reg, val);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
+FullO3CPU::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
 {
    cpuStats.ccRegfileWrites++;
    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1451,61 +1379,53 @@ FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
    regFile.setCCReg(phys_reg, val);
 }

-template <class Impl>
 TheISA::PCState
-FullO3CPU<Impl>::pcState(ThreadID tid)
+FullO3CPU::pcState(ThreadID tid)
 {
    return commit.pcState(tid);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
+FullO3CPU::pcState(const TheISA::PCState &val, ThreadID tid)
 {
    commit.pcState(val, tid);
 }

-template <class Impl>
 Addr
-FullO3CPU<Impl>::instAddr(ThreadID tid)
+FullO3CPU::instAddr(ThreadID tid)
 {
    return commit.instAddr(tid);
 }

-template <class Impl>
 Addr
-FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
+FullO3CPU::nextInstAddr(ThreadID tid)
 {
    return commit.nextInstAddr(tid);
 }

-template <class Impl>
 MicroPC
-FullO3CPU<Impl>::microPC(ThreadID tid)
+FullO3CPU::microPC(ThreadID tid)
 {
    return commit.microPC(tid);
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::squashFromTC(ThreadID tid)
+FullO3CPU::squashFromTC(ThreadID tid)
 {
-    this->thread[tid]->noSquashFromTC = true;
-    this->commit.generateTCEvent(tid);
+    thread[tid]->noSquashFromTC = true;
+    commit.generateTCEvent(tid);
 }

-template <class Impl>
-typename FullO3CPU<Impl>::ListIt
-FullO3CPU<Impl>::addInst(const O3DynInstPtr &inst)
+FullO3CPU::ListIt
+FullO3CPU::addInst(const O3DynInstPtr &inst)
 {
    instList.push_back(inst);

    return --(instList.end());
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::instDone(ThreadID tid, const O3DynInstPtr &inst)
+FullO3CPU::instDone(ThreadID tid, const O3DynInstPtr &inst)
 {
    // Keep an instruction count.
    if (!inst->isMicroop() || inst->isLastMicroop()) {
@@ -1523,9 +1443,8 @@ FullO3CPU<Impl>::instDone(ThreadID tid, const O3DynInstPtr &inst)
    probeInstCommit(inst->staticInst, inst->instAddr());
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::removeFrontInst(const O3DynInstPtr &inst)
+FullO3CPU::removeFrontInst(const O3DynInstPtr &inst)
 {
    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
            "[sn:%lli]\n",
@@ -1537,9 +1456,8 @@ FullO3CPU<Impl>::removeFrontInst(const O3DynInstPtr &inst)
    removeList.push(inst->getInstListIt());
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
+FullO3CPU::removeInstsNotInROB(ThreadID tid)
 {
    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
            " list.\n", tid);
@@ -1582,9 +1500,8 @@ FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
+FullO3CPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
 {
    assert(!instList.empty());

@@ -1611,9 +1528,8 @@ FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
    }
 }

-template <class Impl>
-inline void
-FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
+void
+FullO3CPU::squashInstIt(const ListIt &instIt, ThreadID tid)
 {
    if ((*instIt)->threadNumber == tid) {
        DPRINTF(O3CPU, "Squashing instruction, "
@@ -1632,9 +1548,8 @@ FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::cleanUpRemovedInsts()
+FullO3CPU::cleanUpRemovedInsts()
 {
    while (!removeList.empty()) {
        DPRINTF(O3CPU, "Removing instruction, "
@@ -1651,16 +1566,14 @@ FullO3CPU<Impl>::cleanUpRemovedInsts()
    removeInstsThisCycle = false;
 }
 /*
-template <class Impl>
 void
-FullO3CPU<Impl>::removeAllInsts()
+FullO3CPU::removeAllInsts()
 {
    instList.clear();
 }
 */
-template <class Impl>
 void
-FullO3CPU<Impl>::dumpInsts()
+FullO3CPU::dumpInsts()
 {
    int num = 0;

@@ -1679,16 +1592,14 @@ FullO3CPU<Impl>::dumpInsts()
    }
 }
 /*
-template <class Impl>
 void
-FullO3CPU<Impl>::wakeDependents(const O3DynInstPtr &inst)
+FullO3CPU::wakeDependents(const O3DynInstPtr &inst)
 {
    iew.wakeDependents(inst);
 }
 */
-template <class Impl>
 void
-FullO3CPU<Impl>::wakeCPU()
+FullO3CPU::wakeCPU()
 {
    if (activityRec.active() || tickEvent.scheduled()) {
        DPRINTF(Activity, "CPU already running.\n");
@@ -1708,22 +1619,20 @@ FullO3CPU<Impl>::wakeCPU()
    schedule(tickEvent, clockEdge());
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::wakeup(ThreadID tid)
+FullO3CPU::wakeup(ThreadID tid)
 {
-    if (this->thread[tid]->status() != ThreadContext::Suspended)
+    if (thread[tid]->status() != ThreadContext::Suspended)
        return;

-    this->wakeCPU();
+    wakeCPU();

    DPRINTF(Quiesce, "Suspended Processor woken\n");
-    this->threadContexts[tid]->activate();
+    threadContexts[tid]->activate();
 }

-template <class Impl>
 ThreadID
-FullO3CPU<Impl>::getFreeTid()
+FullO3CPU::getFreeTid()
 {
    for (ThreadID tid = 0; tid < numThreads; tid++) {
        if (!tids[tid]) {
@@ -1735,9 +1644,8 @@ FullO3CPU<Impl>::getFreeTid()
    return InvalidThreadID;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::updateThreadPriority()
+FullO3CPU::updateThreadPriority()
 {
    if (activeThreads.size() > 1) {
        //DEFAULT TO ROUND ROBIN SCHEME
@@ -1752,9 +1660,8 @@ FullO3CPU<Impl>::updateThreadPriority()
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::addThreadToExitingList(ThreadID tid)
+FullO3CPU::addThreadToExitingList(ThreadID tid)
 {
    DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);

@@ -1772,16 +1679,14 @@ FullO3CPU<Impl>::addThreadToExitingList(ThreadID tid)
    exitingThreads.emplace(std::make_pair(tid, false));
 }

-template <class Impl>
 bool
-FullO3CPU<Impl>::isThreadExiting(ThreadID tid) const
+FullO3CPU::isThreadExiting(ThreadID tid) const
 {
    return exitingThreads.count(tid) == 1;
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid)
+FullO3CPU::scheduleThreadExitEvent(ThreadID tid)
 {
    assert(exitingThreads.count(tid) == 1);

@@ -1800,9 +1705,8 @@ FullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid)
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::exitThreads()
+FullO3CPU::exitThreads()
 {
    // there must be at least one thread trying to exit
    assert(exitingThreads.size() > 0);
@@ -1824,9 +1728,8 @@ FullO3CPU<Impl>::exitThreads()
    }
 }

-template <class Impl>
 void
-FullO3CPU<Impl>::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
+FullO3CPU::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
     HtmFailureFaultCause cause)
 {
    const Addr addr = 0x0ul;
@@ -1835,15 +1738,15 @@ FullO3CPU<Impl>::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
      Request::PHYSICAL|Request::STRICT_ORDER|Request::HTM_ABORT;

    // O3-specific actions
-    this->iew.ldstQueue.resetHtmStartsStops(tid);
-    this->commit.resetHtmStartsStops(tid);
+    iew.ldstQueue.resetHtmStartsStops(tid);
+    commit.resetHtmStartsStops(tid);

    // notify l1 d-cache (ruby) that core has aborted transaction
    RequestPtr req =
        std::make_shared<Request>(addr, size, flags, _dataRequestorId);

    req->taskId(taskId());
-    req->setContext(this->thread[tid]->contextId());
+    req->setContext(thread[tid]->contextId());
    req->setHtmAbortCause(cause);

    assert(req->isHTMAbort());
@@ -1855,10 +1758,7 @@ FullO3CPU<Impl>::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
    abort_pkt->setHtmTransactional(htm_uid);

    // TODO include correct error handling here
-    if (!this->iew.ldstQueue.getDataPort().sendTimingReq(abort_pkt)) {
+    if (!iew.ldstQueue.getDataPort().sendTimingReq(abort_pkt)) {
        panic("HTM abort signal was not sent to the memory subsystem.");
    }
 }
-
-// Forward declaration of FullO3CPU.
-template class FullO3CPU<O3CPUImpl>;
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -86,15 +86,10 @@ class Process;
 * within it, as well as all of the time buffers between stages.  The
 * tick() function for the CPU is defined here.
 */
-template <class Impl>
 class FullO3CPU : public BaseCPU
 {
  public:
-    // Typedefs from the Impl here.
-    typedef O3ThreadState<Impl> ImplState;
-    typedef O3ThreadState<Impl> Thread;
-
-    typedef typename std::list<O3DynInstPtr>::iterator ListIt;
+    typedef std::list<O3DynInstPtr>::iterator ListIt;

    friend class O3ThreadContext;

@@ -168,8 +163,6 @@ class FullO3CPU : public BaseCPU
  public:
    /** Constructs a CPU with the given parameters. */
    FullO3CPU(const DerivO3CPUParams &params);
-    /** Destructor. */
-    ~FullO3CPU();

    ProbePointArg<PacketPtr> *ppInstAccessComplete;
    ProbePointArg<std::pair<O3DynInstPtr, PacketPtr> > *ppDataAccessComplete;
@@ -445,7 +438,7 @@ class FullO3CPU : public BaseCPU
    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);

    /** Removes the instruction pointed to by the iterator. */
-    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
+    void squashInstIt(const ListIt &instIt, ThreadID tid);

    /** Cleans up all instructions on the remove list. */
    void cleanUpRemovedInsts();
@@ -606,7 +599,7 @@ class FullO3CPU : public BaseCPU
    System *system;

    /** Pointers to all of the threads in the CPU. */
-    std::vector<Thread *> thread;
+    std::vector<O3ThreadState<O3CPUImpl> *> thread;

    /** Threads Scheduled to Enter CPU */
    std::list<int> cpuWaitList;
@@ -638,27 +631,27 @@ class FullO3CPU : public BaseCPU
    /** CPU read function, forwards read to LSQ. */
    Fault read(LSQRequest* req, int load_idx)
    {
-        return this->iew.ldstQueue.read(req, load_idx);
+        return iew.ldstQueue.read(req, load_idx);
    }

    /** CPU write function, forwards write to LSQ. */
    Fault write(LSQRequest* req, uint8_t *data, int store_idx)
    {
-        return this->iew.ldstQueue.write(req, data, store_idx);
+        return iew.ldstQueue.write(req, data, store_idx);
    }

    /** Used by the fetch unit to get a hold of the instruction port. */
    Port &
    getInstPort() override
    {
-        return this->fetch.getInstPort();
+        return fetch.getInstPort();
    }

    /** Get the dcache port (used to find block size for translations). */
    Port &
    getDataPort() override
    {
-        return this->iew.ldstQueue.getDataPort();
+        return iew.ldstQueue.getDataPort();
    }

    struct FullO3CPUStats : public Stats::Group
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -56,8 +56,7 @@
 // we open up the entire namespace std
 using std::list;

-DefaultDecode::DefaultDecode(FullO3CPU<O3CPUImpl> *_cpu,
-        const DerivO3CPUParams &params)
+DefaultDecode::DefaultDecode(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : cpu(_cpu),
      renameToDecodeDelay(params.renameToDecodeDelay),
      iewToDecodeDelay(params.iewToDecodeDelay),
@@ -115,7 +114,7 @@ DefaultDecode::name() const
    return cpu->name() + ".decode";
 }

-DefaultDecode::DecodeStats::DecodeStats(FullO3CPU<O3CPUImpl> *cpu)
+DefaultDecode::DecodeStats::DecodeStats(FullO3CPU *cpu)
    : Stats::Group(cpu, "decode"),
      ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
               "Number of cycles decode is idle"),
@@ -436,7 +435,7 @@ DefaultDecode::updateStatus()

            DPRINTF(Activity, "Activating stage.\n");

-            cpu->activateStage(FullO3CPU<O3CPUImpl>::DecodeIdx);
+            cpu->activateStage(FullO3CPU::DecodeIdx);
        }
    } else {
        // If it's not unblocking, then decode will not have any internal
@@ -445,7 +444,7 @@ DefaultDecode::updateStatus()
            _status = Inactive;
            DPRINTF(Activity, "Deactivating stage.\n");

-            cpu->deactivateStage(FullO3CPU<O3CPUImpl>::DecodeIdx);
+            cpu->deactivateStage(FullO3CPU::DecodeIdx);
        }
    }
 }
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -52,7 +52,6 @@

 struct DerivO3CPUParams;

-template <class Impl>
 class FullO3CPU;

 /**
@@ -94,7 +93,7 @@ class DefaultDecode

  public:
    /** DefaultDecode constructor. */
-    DefaultDecode(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    DefaultDecode(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    void startupStage();

@@ -201,7 +200,7 @@ class DefaultDecode
  private:
    // Interfaces to objects outside of decode.
    /** CPU interface. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Time buffer interface. */
    TimeBuffer<O3Comm::TimeStruct> *timeBuffer;
@@ -292,7 +291,7 @@ class DefaultDecode

    struct DecodeStats : public Stats::Group
    {
-        DecodeStats(FullO3CPU<O3CPUImpl> *cpu);
+        DecodeStats(FullO3CPU *cpu);

        /** Stat for total number of idle cycles. */
        Stats::Scalar idleCycles;
--- a/src/cpu/o3/deriv.hh
+++ b/src/cpu/o3/deriv.hh
@@ -30,13 +30,13 @@
 #define __CPU_O3_DERIV_HH__

 #include "cpu/o3/cpu.hh"
-#include "cpu/o3/impl.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "params/DerivO3CPU.hh"

-class DerivO3CPU : public FullO3CPU<O3CPUImpl>
+class DerivO3CPU : public FullO3CPU
 {
  public:
-    DerivO3CPU(const DerivO3CPUParams &p) : FullO3CPU<O3CPUImpl>(p) {}
+    DerivO3CPU(const DerivO3CPUParams &p) : FullO3CPU(p) {}
 };

 #endif // __CPU_O3_DERIV_HH__
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -49,7 +49,7 @@
 BaseO3DynInst::BaseO3DynInst(const StaticInstPtr &static_inst,
                             const StaticInstPtr &_macroop,
                             TheISA::PCState _pc, TheISA::PCState pred_pc,
-                             InstSeqNum seq_num, FullO3CPU<O3CPUImpl> *_cpu)
+                             InstSeqNum seq_num, FullO3CPU *_cpu)
    : seqNum(seq_num), staticInst(static_inst), cpu(_cpu), pc(_pc),
      regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
      predPC(pred_pc), macroop(_macroop)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -77,7 +77,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
    /** BaseDynInst constructor given a binary instruction. */
    BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
            &macroop, TheISA::PCState pc, TheISA::PCState predPC,
-            InstSeqNum seq_num, FullO3CPU<O3CPUImpl> *cpu);
+            InstSeqNum seq_num, FullO3CPU *cpu);

    /** BaseDynInst constructor given a static inst pointer. */
    BaseO3DynInst(const StaticInstPtr &_staticInst,
@@ -101,7 +101,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
    const StaticInstPtr staticInst;

    /** Pointer to the Impl's CPU object. */
-    FullO3CPU<O3CPUImpl> *cpu = nullptr;
+    FullO3CPU *cpu = nullptr;

    BaseCPU *getCpuPtr() { return cpu; }

--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -70,14 +70,12 @@
 #include "sim/full_system.hh"
 #include "sim/system.hh"

-DefaultFetch::IcachePort::IcachePort(DefaultFetch *_fetch,
-            FullO3CPU<O3CPUImpl>* _cpu) :
+DefaultFetch::IcachePort::IcachePort(DefaultFetch *_fetch, FullO3CPU *_cpu) :
        RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
 {}


-DefaultFetch::DefaultFetch(FullO3CPU<O3CPUImpl> *_cpu,
-        const DerivO3CPUParams &params)
+DefaultFetch::DefaultFetch(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : fetchPolicy(params.smtFetchPolicy),
      cpu(_cpu),
      branchPred(nullptr),
@@ -155,7 +153,7 @@ DefaultFetch::regProbePoints()
 }

 DefaultFetch::FetchStatGroup::FetchStatGroup(
-        FullO3CPU<O3CPUImpl> *cpu, DefaultFetch *fetch)
+        FullO3CPU *cpu, DefaultFetch *fetch)
    : Stats::Group(cpu, "fetch"),
    ADD_STAT(icacheStallCycles, Stats::Units::Cycle::get(),
             "Number of cycles fetch is stalled on an Icache miss"),
@@ -476,7 +474,7 @@ DefaultFetch::switchToActive()
    if (_status == Inactive) {
        DPRINTF(Activity, "Activating stage.\n");

-        cpu->activateStage(FullO3CPU<O3CPUImpl>::FetchIdx);
+        cpu->activateStage(FullO3CPU::FetchIdx);

        _status = Active;
    }
@@ -488,7 +486,7 @@ DefaultFetch::switchToInactive()
    if (_status == Active) {
        DPRINTF(Activity, "Deactivating stage.\n");

-        cpu->deactivateStage(FullO3CPU<O3CPUImpl>::FetchIdx);
+        cpu->deactivateStage(FullO3CPU::FetchIdx);

        _status = Inactive;
    }
@@ -805,7 +803,7 @@ DefaultFetch::updateFetchStatus()
                            "completion\n",tid);
                }

-                cpu->activateStage(FullO3CPU<O3CPUImpl>::FetchIdx);
+                cpu->activateStage(FullO3CPU::FetchIdx);
            }

            return Active;
@@ -816,7 +814,7 @@ DefaultFetch::updateFetchStatus()
    if (_status == Active) {
        DPRINTF(Activity, "Deactivating stage.\n");

-        cpu->deactivateStage(FullO3CPU<O3CPUImpl>::FetchIdx);
+        cpu->deactivateStage(FullO3CPU::FetchIdx);
    }

    return Inactive;
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -59,7 +59,6 @@
 #include "sim/probe/probe.hh"

 struct DerivO3CPUParams;
-template <class Impl>
 class FullO3CPU;

 /**
@@ -84,7 +83,7 @@ class DefaultFetch

      public:
        /** Default constructor. */
-        IcachePort(DefaultFetch *_fetch, FullO3CPU<O3CPUImpl>* _cpu);
+        IcachePort(DefaultFetch *_fetch, FullO3CPU *_cpu);

      protected:

@@ -197,7 +196,7 @@ class DefaultFetch

  public:
    /** DefaultFetch constructor. */
-    DefaultFetch(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    DefaultFetch(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    /** Returns the name of fetch. */
    std::string name() const;
@@ -383,7 +382,7 @@ class DefaultFetch

  private:
    /** Pointer to the O3CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Time buffer interface. */
    TimeBuffer<O3Comm::TimeStruct> *timeBuffer;
@@ -525,7 +524,7 @@ class DefaultFetch
  protected:
    struct FetchStatGroup : public Stats::Group
    {
-        FetchStatGroup(FullO3CPU<O3CPUImpl> *cpu, DefaultFetch *fetch);
+        FetchStatGroup(FullO3CPU *cpu, DefaultFetch *fetch);
        // @todo: Consider making these
        // vectors and tracking on a per thread basis.
        /** Stat for total number of cycles stalled due to an icache miss. */
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -59,8 +59,7 @@
 #include "debug/O3PipeView.hh"
 #include "params/DerivO3CPU.hh"

-DefaultIEW::DefaultIEW(FullO3CPU<O3CPUImpl> *_cpu,
-        const DerivO3CPUParams &params)
+DefaultIEW::DefaultIEW(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : issueToExecQueue(params.backComSize, params.forwardComSize),
      cpu(_cpu),
      instQueue(_cpu, this, params),
@@ -137,7 +136,7 @@ DefaultIEW::regProbePoints()
            cpu->getProbeManager(), "ToCommit");
 }

-DefaultIEW::IEWStats::IEWStats(FullO3CPU<O3CPUImpl> *cpu)
+DefaultIEW::IEWStats::IEWStats(FullO3CPU *cpu)
    : Stats::Group(cpu),
    ADD_STAT(idleCycles, Stats::Units::Cycle::get(),
             "Number of cycles IEW is idle"),
@@ -211,8 +210,7 @@ DefaultIEW::IEWStats::IEWStats(FullO3CPU<O3CPUImpl> *cpu)
    wbFanout = producerInst / consumerInst;
 }

-DefaultIEW::IEWStats::ExecutedInstStats::ExecutedInstStats(
-        FullO3CPU<O3CPUImpl> *cpu)
+DefaultIEW::IEWStats::ExecutedInstStats::ExecutedInstStats(FullO3CPU *cpu)
    : Stats::Group(cpu),
    ADD_STAT(numInsts, Stats::Units::Count::get(),
             "Number of executed instructions"),
@@ -282,7 +280,7 @@ DefaultIEW::startupStage()
        cpu->checker->setDcachePort(&ldstQueue.getDataPort());
    }

-    cpu->activateStage(FullO3CPU<O3CPUImpl>::IEWIdx);
+    cpu->activateStage(FullO3CPU::IEWIdx);
 }

 void
@@ -827,14 +825,14 @@ void
 DefaultIEW::activateStage()
 {
    DPRINTF(Activity, "Activating stage.\n");
-    cpu->activateStage(FullO3CPU<O3CPUImpl>::IEWIdx);
+    cpu->activateStage(FullO3CPU::IEWIdx);
 }

 void
 DefaultIEW::deactivateStage()
 {
    DPRINTF(Activity, "Deactivating stage.\n");
-    cpu->deactivateStage(FullO3CPU<O3CPUImpl>::IEWIdx);
+    cpu->deactivateStage(FullO3CPU::IEWIdx);
 }

 void
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -120,7 +120,7 @@ class DefaultIEW

  public:
    /** Constructs a DefaultIEW with the given parameters. */
-    DefaultIEW(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    DefaultIEW(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    /** Returns the name of the DefaultIEW stage. */
    std::string name() const;
@@ -338,7 +338,7 @@ class DefaultIEW

  private:
    /** CPU pointer. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Records if IEW has written to the time buffer this cycle, so that the
     * CPU can deschedule itself if there is no activity.
@@ -415,7 +415,7 @@ class DefaultIEW

    struct IEWStats : public Stats::Group
    {
-        IEWStats(FullO3CPU<O3CPUImpl> *cpu);
+        IEWStats(FullO3CPU *cpu);

        /** Stat for total number of idle cycles. */
        Stats::Scalar idleCycles;
@@ -451,7 +451,7 @@ class DefaultIEW

        struct ExecutedInstStats : public Stats::Group
        {
-            ExecutedInstStats(FullO3CPU<O3CPUImpl> *cpu);
+            ExecutedInstStats(FullO3CPU *cpu);

            /** Stat for total number of executed instructions. */
            Stats::Scalar numInsts;
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -78,8 +78,8 @@ InstructionQueue::FUCompletion::description() const
    return "Functional unit completion";
 }

-InstructionQueue::InstructionQueue(FullO3CPU<O3CPUImpl> *cpu_ptr,
-        DefaultIEW *iew_ptr, const DerivO3CPUParams &params)
+InstructionQueue::InstructionQueue(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
+        const DerivO3CPUParams &params)
    : cpu(cpu_ptr),
      iewStage(iew_ptr),
      fuPool(params.fuPool),
@@ -167,8 +167,7 @@ InstructionQueue::name() const
    return cpu->name() + ".iq";
 }

-InstructionQueue::IQStats::IQStats(FullO3CPU<O3CPUImpl> *cpu,
-        const unsigned &total_width)
+InstructionQueue::IQStats::IQStats(FullO3CPU *cpu, const unsigned &total_width)
    : Stats::Group(cpu),
    ADD_STAT(instsAdded, Stats::Units::Count::get(),
             "Number of instructions added to the IQ (excludes non-spec)"),
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -66,8 +66,6 @@ struct DerivO3CPUParams;
 class FUPool;
 class MemInterface;
 class DefaultIEW;
-
-template <class Impl>
 class FullO3CPU;

 /**
@@ -122,7 +120,7 @@ class InstructionQueue
    };

    /** Constructs an IQ. */
-    InstructionQueue(FullO3CPU<O3CPUImpl> *cpu_ptr, DefaultIEW *iew_ptr,
+    InstructionQueue(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
            const DerivO3CPUParams &params);

    /** Destructs the IQ. */
@@ -279,7 +277,7 @@ class InstructionQueue
    /////////////////////////

    /** Pointer to the CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Cache interface. */
    MemInterface *dcacheInterface;
@@ -476,7 +474,7 @@ class InstructionQueue

    struct IQStats : public Stats::Group
    {
-        IQStats(FullO3CPU<O3CPUImpl> *cpu, const unsigned &total_width);
+        IQStats(FullO3CPU *cpu, const unsigned &total_width);
        /** Stat for number of instructions added. */
        Stats::Scalar instsAdded;
        /** Stat for number of non-speculative instructions added. */
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -68,11 +68,11 @@ LSQ::LSQSenderState::contextId()
    return inst->contextId();
 }

-LSQ::DcachePort::DcachePort(LSQ *_lsq, FullO3CPU<O3CPUImpl> *_cpu) :
+LSQ::DcachePort::DcachePort(LSQ *_lsq, FullO3CPU *_cpu) :
    RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu)
 {}

-LSQ::LSQ(FullO3CPU<O3CPUImpl> *cpu_ptr, DefaultIEW *iew_ptr,
+LSQ::LSQ(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
        const DerivO3CPUParams &params)
    : cpu(cpu_ptr), iewStage(iew_ptr),
      _cacheBlocked(false),
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -62,9 +62,7 @@

 struct DerivO3CPUParams;

-template <class Impl>
 class FullO3CPU;
-
 class DefaultIEW;
 class LSQUnit;

@@ -124,11 +122,11 @@ class LSQ

        /** Pointer to LSQ. */
        LSQ *lsq;
-        FullO3CPU<O3CPUImpl> *cpu;
+        FullO3CPU *cpu;

      public:
        /** Default constructor. */
-        DcachePort(LSQ *_lsq, FullO3CPU<O3CPUImpl> *_cpu);
+        DcachePort(LSQ *_lsq, FullO3CPU *_cpu);

      protected:

@@ -782,7 +780,7 @@ class LSQ
    };

    /** Constructs an LSQ with the given parameters. */
-    LSQ(FullO3CPU<O3CPUImpl> *cpu_ptr, DefaultIEW *iew_ptr,
+    LSQ(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
            const DerivO3CPUParams &params);

    /** Returns the name of the LSQ. */
@@ -992,7 +990,7 @@ class LSQ
                      const std::vector<bool>& byte_enable);

    /** The CPU pointer. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** The IEW stage pointer. */
    DefaultIEW *iewStage;
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -204,7 +204,7 @@ LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
 }

 void
-LSQUnit::init(FullO3CPU<O3CPUImpl> *cpu_ptr, DefaultIEW *iew_ptr,
+LSQUnit::init(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
        const DerivO3CPUParams &params, LSQ *lsq_ptr, unsigned id)
 {
    lsqID = id;
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -224,7 +224,7 @@ class LSQUnit
    }

    /** Initializes the LSQ unit with the specified number of entries. */
-    void init(FullO3CPU<O3CPUImpl> *cpu_ptr, DefaultIEW *iew_ptr,
+    void init(FullO3CPU *cpu_ptr, DefaultIEW *iew_ptr,
            const DerivO3CPUParams &params, LSQ *lsq_ptr, unsigned id);

    /** Returns the name of the LSQ unit. */
@@ -394,7 +394,7 @@ class LSQUnit

  private:
    /** Pointer to the CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Pointer to the IEW stage. */
    DefaultIEW *iewStage;
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -83,8 +83,7 @@ MemDepUnit::~MemDepUnit()
 }

 void
-MemDepUnit::init(const DerivO3CPUParams &params, ThreadID tid,
-        FullO3CPU<O3CPUImpl> *cpu)
+MemDepUnit::init(const DerivO3CPUParams &params, ThreadID tid, FullO3CPU *cpu)
 {
    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);

--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -69,8 +69,6 @@ struct SNHash
 struct DerivO3CPUParams;

 class InstructionQueue;
-
-template <class Impl>
 class FullO3CPU;

 /**
@@ -103,8 +101,7 @@ class MemDepUnit
    std::string name() const { return _name; }

    /** Initializes the unit with parameters and a thread id. */
-    void init(const DerivO3CPUParams &params, ThreadID tid,
-            FullO3CPU<O3CPUImpl> *cpu);
+    void init(const DerivO3CPUParams &params, ThreadID tid, FullO3CPU *cpu);

    /** Determine if we are drained. */
    bool isDrained() const;
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -58,7 +58,7 @@ ElasticTrace::ElasticTrace(const ElasticTraceParams &params)
       traceVirtAddr(params.traceVirtAddr),
       stats(this)
 {
-    cpu = dynamic_cast<FullO3CPU<O3CPUImpl>*>(params.manager);
+    cpu = dynamic_cast<FullO3CPU *>(params.manager);
    const BaseISA::RegClasses &regClasses =
        cpu->getContext(0)->getIsaPtr()->regClasses();
    zeroReg = regClasses.at(IntRegClass).zeroReg();
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -62,7 +62,6 @@
 #include "sim/eventq.hh"
 #include "sim/probe/probe.hh"

-template <class Impl>
 class FullO3CPU;

 /**
@@ -370,7 +369,7 @@ class ElasticTrace : public ProbeListenerObject
    const bool traceVirtAddr;

    /** Pointer to the O3CPU that is this listener's parent a.k.a. manager */
-    FullO3CPU<O3CPUImpl>* cpu;
+    FullO3CPU *cpu;

    /**
     * Add a record to the dependency trace depTrace which is a sequential
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -52,8 +52,7 @@
 #include "debug/Rename.hh"
 #include "params/DerivO3CPU.hh"

-DefaultRename::DefaultRename(FullO3CPU<O3CPUImpl> *_cpu,
-        const DerivO3CPUParams &params)
+DefaultRename::DefaultRename(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : cpu(_cpu),
      iewToRenameDelay(params.iewToRenameDelay),
      decodeToRenameDelay(params.decodeToRenameDelay),
@@ -840,7 +839,7 @@ DefaultRename::updateStatus()

            DPRINTF(Activity, "Activating stage.\n");

-            cpu->activateStage(FullO3CPU<O3CPUImpl>::RenameIdx);
+            cpu->activateStage(FullO3CPU::RenameIdx);
        }
    } else {
        // If it's not unblocking, then rename will not have any internal
@@ -849,7 +848,7 @@ DefaultRename::updateStatus()
            _status = Inactive;
            DPRINTF(Activity, "Deactivating stage.\n");

-            cpu->deactivateStage(FullO3CPU<O3CPUImpl>::RenameIdx);
+            cpu->deactivateStage(FullO3CPU::RenameIdx);
        }
    }
 }
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -121,7 +121,7 @@ class DefaultRename

  public:
    /** DefaultRename constructor. */
-    DefaultRename(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    DefaultRename(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    /** Returns the name of rename. */
    std::string name() const;
@@ -317,7 +317,7 @@ class DefaultRename
    std::list<RenameHistory> historyBuffer[O3MaxThreads];

    /** Pointer to CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Pointer to main time buffer used for backwards communication. */
    TimeBuffer<O3Comm::TimeStruct> *timeBuffer;
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -49,7 +49,7 @@
 #include "debug/ROB.hh"
 #include "params/DerivO3CPU.hh"

-ROB::ROB(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params)
+ROB::ROB(FullO3CPU *_cpu, const DerivO3CPUParams &params)
    : robPolicy(params.smtROBPolicy),
      cpu(_cpu),
      numEntries(params.numROBEntries),
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -55,7 +55,6 @@
 #include "cpu/reg_class.hh"
 #include "enums/SMTQueuePolicy.hh"

-template <class Impl>
 class FullO3CPU;

 struct DerivO3CPUParams;
@@ -89,7 +88,7 @@ class ROB
     *  @param _cpu   The cpu object pointer.
     *  @param params The cpu params including several ROB-specific parameters.
     */
-    ROB(FullO3CPU<O3CPUImpl> *_cpu, const DerivO3CPUParams &params);
+    ROB(FullO3CPU *_cpu, const DerivO3CPUParams &params);

    std::string name() const;

@@ -266,7 +265,7 @@ class ROB
    void resetState();

    /** Pointer to the CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    /** Active Threads in CPU */
    std::list<ThreadID> *activeThreads;
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -64,7 +64,7 @@ class O3ThreadContext : public ThreadContext
 {
  public:
   /** Pointer to the CPU. */
-    FullO3CPU<O3CPUImpl> *cpu;
+    FullO3CPU *cpu;

    bool
    schedule(PCEvent *e) override
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -67,7 +67,7 @@ struct O3ThreadState : public ThreadState

  private:
    /** Pointer to the CPU. */
-    FullO3CPU<Impl> *cpu;
+    FullO3CPU *cpu;

  public:
    PCEventQueue pcEventQueue;
@@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState
    /** Pointer to the hardware transactional memory checkpoint. */
    std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;

-    O3ThreadState(FullO3CPU<Impl> *_cpu, int _thread_num, Process *_process)
-        : ThreadState(_cpu, _thread_num, _process), cpu(_cpu),
+    O3ThreadState(FullO3CPU *_cpu, int _thread_num, Process *_process)
+        : ThreadState((BaseCPU *)_cpu, _thread_num, _process), cpu(_cpu),
          comInstEventQueue("instruction-based event queue"),
          noSquashFromTC(false), trapPending(false), tc(nullptr)
    {