Commit Graph

14908 Commits

Author SHA1 Message Date
Giacomo Travaglini
07b6f4261c arch-arm: Add undefined helper to ArmStaticInst
In this way we can generate an Undefined Instruction fault
from the instruction object without requiring to access its
menmonic or opcode

This is generalizing the existing disabledFault helper

Change-Id: Ib7dec9399f142c35d75057f37ab53cce102fa01e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61671
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2022-07-28 13:24:02 +00:00
Giacomo Travaglini
25bdb73b9f arch-arm: Generate MSR/MRS iss within trapping logic
The iss field is only used when the MSR/MRS instruction
gets trapped. Rather than generating it at decode time,
we generate the value within the trap method instead

This avoids the confusion of having a MSR/MRS register
instruction storing an immediate field

Later patches will change this even further by generating the
iss field on the fly ONLY if the instruction gets trapped

Change-Id: I97fdcf54d9643ea79a1f9d052073320ee68109fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61670
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2022-07-28 13:24:02 +00:00
Giacomo Travaglini
6217ac737b arch-arm: Overload decodeAArch64SysReg to accept a MiscRegNum64
Overload decodeAArch64SysReg to directly accept a MiscRegNum64

Change-Id: I43c1dae6c0e382c03612f4ce4fc89aadddf30fd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61669
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-28 13:24:02 +00:00
Gabe Black
ba5a017d9a cpu-o3: Remove TheISA:: types from forwardOldRegs.
Use information from the registers' RegClass-es and the generic getReg
and setReg API to forward the registers value without having to refer to
the register class constant/index, or the type of complex registers.

Change-Id: I0426a606185edc0aabbf4b77c825b618b4640590
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50248
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-07-27 21:55:47 +00:00
Gabe Black
87acb97762 cpu-minor: Use the << operator in minorTraceInst.
Use that to print the RegIds of an inst directly, without having to pass
around the register class vector.

Change-Id: I6e5b06518f4826a1e4e8589c5ed095609d3d02b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49809
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
Maintainer: ZHENGRONG WANG <seanyukigeek@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 20:28:48 +00:00
Gabe Black
a46b7c99c8 cpu: Revamp the RegId << operator.
Now that we have a pointer to the actual RegClass the RegId is
associated with, we can use it's regName method to pretty print the
RegId for us. This gets rid of the redundant print method for RegId.

Also, replace the default register printing method with the
implementation in the << operator, which is more descriptive.

Change-Id: I00e93032ddea77e167ca13e54b370de7210f1a2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49808
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 20:28:37 +00:00
Gabe Black
654451c2be arch,cpu: Keep a RegClass pointer in RegId instead of a RegClassType.
This makes it easy to get access to the RegClass that goes with a
register without having to look it up in a separate structure.

Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49786
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 13:54:32 +00:00
Gabe Black
45cf2e3c34 arch: Minimize use of RegClassType constants and the RegId constructor.
These are global values which prevent making register types ISA
specific.

Change-Id: I513adcae5ad316122c24f25a9e01b9974629510f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49785
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 10:59:07 +00:00
Zhantong Qiu
0bcc2e5249 stdlib: Allow set_se_binary_workload to take input parameters
This commit added two paramaters in the set_se_binary_workload to pass
input parameters for the binary.
The "arguments" object allows users to pass in arugments in a list.
The "stdin_file" object allows users to pass in input file as a
Resource.
This commit also created a local variable "binary_path" to save the
return object of "binary.get_local_path()".

Note:
These new parameters were tested and passed in 4 cases:
1. only passing in (Resource/CustomResource) binary
2. passing in (CustomResource) binary and input_file
3. passing in (CustomResource) binary and argument(no input file
 directory included)
4. passing in (CustomResource) binary and argument(with input file
 directory included)

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1242

Change-Id: I6433a349f7ecb5d630c7cdbe7268ff18915bf23f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61609
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-07-26 20:42:04 +00:00
Gabe Black
70289e72cd arch,cpu: Store pointers to RegClass-es instead of instances.
This lets us put the actual RegClass-es somewhere else and give them
names.

Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49784
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
2022-07-26 19:37:59 +00:00
Gabe Black
705351768c cpu: Add a [] operator to the RegClass type.
This will create a RegId with the given index.

Change-Id: I2c3e6859fce80ede5cdb70f85d881b514b6babb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49782
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-26 19:37:33 +00:00
Gabe Black
261fd6122e cpu: Use range based for loops to iterate over RegClass-s.
Change-Id: Ie42ad814a5a90cb635fb4f92d46c8a8c6abeb6a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49781
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-07-26 19:37:15 +00:00
Gabe Black
c3a5dad1e8 cpu: Add an iterator type to RegClass.
This will enable it to be used in range based for loops, to iterate over
all the RegIds which are part of a RegClass. This cleans up that sort of
loop a bit, and also makes it less necessary to construct a RegId
directly.

Change-Id: Ia3c2aa5cf4d842465bd0948d174f51a1b92e5e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49780
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-26 19:37:04 +00:00
Eliot Moss
23b2561bf6 cpu: x86: add serialize and fence instructions to the isa
Clarify commented out lines.

Issue-On: https://gem5.atlassian.net/browse/GEM5-1231

Change-Id: I15d685ca233b56e0aece312bc85a9bff0d56e4dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60929
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-07-23 13:25:49 +00:00
Yu-hsin Wang
f6082ba24b scons: Update GRPC dependency flag
In newer version, grpc will depend on abseil cpp library. We need to get
the correct libs flags from pkg-config.

Change-Id: Id0e3225f69428941945d99cbef8a5749a8d45d8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61510
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2022-07-22 01:10:33 +00:00
Joël Porquet-Lupine
011ffb300b python: remove "earlycon" linux option from LupV board
This option doesn't work and triggers a warning by Linux when booting.

To make it work, we need a chosen node containing an `stdout-path`
property in the FDT which currently doesn't exist.

I tried to create via a couple of approaches it but encountered multiple
issues:

1. One can set `stdout-path` to the complete path of the tty device, but
   such path is impossible to get programmatically (unless it's
   hardcoded).
2. One can set `stdout-path` as a reference to a label. While labels are
   possible to generate easily, reference to labels cannot be generated
   with the current FDT library.

So just remove this option for the time being.

Change-Id: I58ad879c0fdf567a812069ae91ebc7d4f8accf13
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61534
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-07-21 23:54:23 +00:00
Joël Porquet-Lupine
e391805d41 python: improve FDT generation in LupV board
Change-Id: Ia28513a844090d12024ae2328f924a9ce6088059
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61533
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-21 23:54:23 +00:00
Joël Porquet-Lupine
d1d7690123 python: update IRQ mapping in LupV board
Match IRQ map of QEMU LupV platform.

Change-Id: I2a17250343032bdebdf92b9a47a3b5f7a9b6b917
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61532
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-21 23:48:20 +00:00
Joël Porquet-Lupine
da3feeef09 python: swap memory addresses of lupio-rng and lupio-sys
Match the same memory map as in QEMU LupV platform.

Change-Id: I0319e6de26c308eb1b2f402fafe5337dba44733d
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61531
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-21 23:48:13 +00:00
Joël Porquet-Lupine
1c6f57cd6d dev: update LupIO-IPI device to latest specs
The specs for the LupIO-IPI device were recently updated. Instead of
providing a single IPI value for each processor, the device now provides
32 individual IPI bits that can be masked and set.

Update device accordingly in gem5.

Change-Id: Ia47cd1c70e073686bc2009d546c80edb0ad58711
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61530
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-21 23:48:04 +00:00
Joël Porquet-Lupine
0800c060d8 dev: Fix cpu/reg decoding logic in multi-instance LupIO devices
The current decoding logic is flawed and complicated to understand.
Using simple division and modulo instead; the compiler is smart enough
to generate efficient code since the divisor is a power of 2.

Change-Id: I95cbb4969e37132343f557e772984a48749731f0
Signed-off-by: Joël Porquet-Lupine <joel@porquet.org>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61529
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-21 23:47:30 +00:00
Ayaz Akram
ba2deb39e3 mem: Update the default HBMCtrl config
This change updates the default HBMCtrl configuration
to not use partitioned queues, as the unified queue
shows better performance than the partitioned and has
been better tested so far.

Change-Id: I44dd407d8d2af52b8dad5861aeb0ae83e3934d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61470
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-21 19:44:14 +00:00
Ayaz Akram
4d8814f637 mem: Add getAddrRanges in HBMCtrl
This change adds a missed function in HBMCtrl to make
sure that XBar connected to the controller can see
the address ranges covered by both HBM pseudo channels

Change-Id: If88edda42b45a66a6517685e091545a5bba6eab9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61469
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-07-21 19:43:57 +00:00
Jui-Min Lee
f5e03741c7 arch-riscv: Make WFI halt the hart
First, this CL modifies the implementation of WFI so it actually put the
calling CPU into sleep.

This CL also adds an id in the IRQ table to represent NMI. This is
because the wakeup path is only implemented on cpu's postInterrupt
function, and it expects an int_num.

We still keep the MISCREG for nmie and nmip instead of merging them into
other ip/ie as that will give the user ability to get/set the nmi
status, which is pretty dangerous.

Change-Id: Idf8a5748990efa20aa9372efa97d3bed2aac82d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-21 06:40:59 +00:00
Alexandru Dutu
1115f81233 gpu-compute: Fix for HSA queue remapping
When a queue is being remapped the write and dispatch
pointers are set to the read pointer. This assumes that
all packets up to the read pointer have been dispatched
and completed.

Change-Id: I4ed0c6c68f16f57c3fb5c3ecba182a43e74078e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61429
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-20 16:26:14 +00:00
Matthew Poremba
af9ecf7920 arch-vega,arch-gcn3: Add support for VCC_HI as scalar source
Currently there is only support for VCC_LO as a scalar source. Add
support for VCC_HI as well. The op selector symbol is also changed to be
vcc_hi/vcc_lo as it is in disassembly from LLVM.

Change-Id: I19ea8e23873049c33ffe2eb4ec8504a18f371c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61329
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-18 17:27:50 +00:00
Kaustav Goswami
4b554f6f03 stdlib: se_binary_workload exits on work items by default
This change makes the method se_binary_workload to exit automatically
when work items are encountered during simulation. This makes it
similar to the method set_kernel_disk_workload in terms of work items.

Change-Id: I8a676e3e174fd65930853b1849e3e0be6a643231
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61311
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-07-15 20:55:24 +00:00
Matthew Poremba
3a73aa3ac1 arch-vega: Implement new VOP2 using VOP3 insts
Vega adds three new VOP2 instructions that may use VOP3 encoding that
are not part of the GCN3 ISA: v_add_u32, v_sub_u32, v_subrev_u32. This
changeset implements those three new instructions to fix errors related
to "invalid encoding" when those instructions are seen.

Tested using srad from Rodinia 3.0 HIP port which compiles a v_add_u32
instruction with VOP3 encoding.

Change-Id: I409a9f72f5c37895c3a0ab7ceb14a4dd121874a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61330
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2022-07-15 14:55:33 +00:00
Mahyar Samani
152ffb0d43 stdlib: Removing incorrect requires.
This change removes call to requires for checking isa_required
in AbstractProcessor.__init__() and
AbstractGeneratorCore.__init__(). The previous calls would cause
incorrect errors when running generators with any isa other than
NULL.

Change-Id: I303f1e48a7d5649bbe19e0f52ace808225a771c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-07-13 22:45:24 +00:00
Matthew Poremba
40077055cf arch-vega: Fix disassembly for two dword VOPC
Calling opSelectorToRegSym in the disassembly for VOPC when there is a
second dword (SDWA, DPP, or Literal) causes a panic as those registers
do not have a string symbol. This is fixed by checking for a second
dword before printing similar to how VOP1, VOP2, SOP1, etc. function.

Change-Id: I97b33e1e45abcf3ff1d0bc5754773b4eee961a98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61269
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-12 19:05:32 +00:00
Gabriel Busnot
43820b0700 misc: Represent Int links as directional edges
Int links are uni-directional in Ruby. This patch make them
unidirectional in the dot representation as well.

Change-Id: I86086d6689bfaa76856b84bf4cac3701d1e5cad9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61010
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-11 09:06:22 +00:00
Gabriel Busnot
1f32846874 python: limit tooltip string length to 16384
Pydot limits the maximum line length to this value

JIRA:https://gem5.atlassian.net/browse/GEM5-1200

Change-Id: I0e6423b79f014695496dad279322304ae10a3978
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61009
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2022-07-11 09:06:22 +00:00
Zhantong Qiu
131f5f033a stdlib: This commit added warning for exit default behavior
This commit imported the warn from m5.util library and added a function
 named "defaultBehaviorWarning" to the exit_event_generators.py file
under src/python/gem5/simulator.

This function takes two string variable and output a warning that
contains a warning about the default behavior, the behavior type,
 and an detail explaination about it.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1235

Change-Id: I54500425eaa1a556769aa1f8ea6b32852694c94d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61189
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-10 16:54:52 +00:00
Jasjeet Rangi
16af1f0cc0 stdlib: Fix KVM required message typo
Change word "unavaiable" to "unavailable".

When kvm_required is set to True in requires() from gem5.utils.requires
and KVM is not available on the host system, print "KVM is required but
is unavailable on this system" instead of ""KVM is required but is
unavaiable on this system".

Change-Id: I483fb75a6a4781560ae338370ba2714fd8737cc6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61169
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-08 16:03:27 +00:00
Jui-Min Lee
b6dcae31ee mem: multi-clients support for SharedMemoryServer
Record the client session with a map instead of a single unique_ptr so
our server can interact with multiple clients at once.

This will also avoid a race condition case where the client thought it
has closed previous connection and is trying to a new one while the
server hasn't clean up the previous entry and raise a fatal error.

Change-Id: Id08154fc4b54d2611629875b3f4e0d66c0e2ed92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61049
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-08 01:14:55 +00:00
ksco
f5d15871f3 arch-riscv: Treat InvalidRegClass as zero register.
Currently the disassembler will print the zero register as ft0, this commit provides a workaround to solve this problem.

Change-Id: Ic8ac3f277dd9ff886dc84a83c022954ad30c47f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61150
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-08 00:09:01 +00:00
ksco
a4a2170409 arch-riscv: Use more precise mnemonics
Change-Id: I520ff63b8ca88e0dab75c03a07f17430fc160ea9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61149
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-08 00:08:43 +00:00
ksco
8fb2dfaa6a arch-riscv: Add K extension
This commit adds part of RISC-V Cryptography Extensions v1.0.1 to gem5. Include the following instructions:

Zbkx:
xperm8: Crossbar permutation (bytes)
xperm4: Crossbar permutation (nibbles)

Zknd:
aes64ds:   AES decrypt final round (RV64)
aes64dsm:  AES decrypt middle round (RV64)
aes64im:   AES Decrypt KeySchedule MixColumns (RV64)
aes64ks1i: AES Key Schedule Instruction 1 (RV64)
aes64ks2:  AES Key Schedule Instruction 2 (RV64)

Zkne:
aes64es:   AES encrypt final round instruction (RV64)
aes64esm:  AES encrypt middle round instruction (RV64)
aes64ks1i: AES Key Schedule Instruction 1 (RV64)
aes64ks2:  AES Key Schedule Instruction 2 (RV64)

Zknh:
sha256sig0: SHA2-256 Sigma0 instruction
sha256sig1: SHA2-256 Sigma1 instruction
sha256sum0: SHA2-256 Sum0 instruction
sha256sum1: SHA2-256 Sum1 instruction
sha512sig0: SHA2-512 Sigma0 instruction (RV64)
sha512sig1: SHA2-512 Sigma1 instruction (RV64)
sha512sum0: SHA2-512 Sum0 instruction (RV64)
sha512sum1: SHA2-512 Sum1 instruction (RV64)

Zksed:
sm4ed: SM4 Encrypt/Decrypt Instruction
sm4ks: SM4 Key Schedule Instruction

Zksh:
sm3p0: SM3 P0 transform
sm3p1: SM3 P1 transform

Change-Id: Ide3e6a4ce903be09dfb3e6b702c9dbcf74a35afb
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60949
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-08 00:08:01 +00:00
Earl Ou
01e99c3c7d systemc: Use debug trace for TlmBridge
Some messages in TlmBridge is too verbose
in the system with many bridges.

Change-Id: I27b30b518877731017bc980a3cd4706807c1ecfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60791
Maintainer: Earl Ou <shunhsingou@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2022-07-07 00:55:33 +00:00
Richard Cooper
f9b57ee4ed mem-ruby: Allow SLICC symbols to have no description.
Updated the SLICC `Symbol` class to return an empty string when its
`desc` property is read.

The SLICC language does not require a symbol to have a `desc` for
protocol generation, but the generation of SLICC HTML documentation
expects a `desc` and will fail if it is not present.

Change-Id: I07cc0ab805520eb74f86c6ea8036abb7354b10a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60870
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-07-06 17:09:46 +00:00
Richard Cooper
b893344b7d mem-ruby: Add descriptions to the CHI DVM symbols.
This commit adds `desc` descriptions to the new symbols introduced
with CHI DVM support. The generation of the SLICC HTML documentation
requires each symbol to have a description, so a build with
`SLICC_HTML=True` will fail without this change.

Change-Id: I06f3bdd33edd1ff6e4bec35b01a460b9359ed9f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60869
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-06 17:09:46 +00:00
Giacomo Travaglini
ccdec1b11d arch-arm: Do not trap SIMD insts to EL1 if in VHE host
Change-Id: I4ea326eead1aec1e013280b599c57f2202901625
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60971
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-05 08:45:01 +00:00
Giacomo Travaglini
343f7b7bf6 arch-arm: Do not trap MISCREG_DC_ZVA_Xt to EL1 if in VHE host
Change-Id: I785be01fcb97b78e0b59f8f9a4f8d150208fa88a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60970
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-05 08:45:01 +00:00
Giacomo Travaglini
ea9620922c arch-arm: Revamp of AArch64 S1 access permission logic
This patch is revamping/simplifying the access permission logic in the
ArmMMU (ArmMMU::s1PermBits64) by matching more closely the Arm
architecture reference manual pseudocode.

It also fixes VHE access permission: previous version was not
considering the EL2&0 translation regime.
Now EL2&0 is handled correctly through the new hasUnprivRegime method

Change-Id: I2689738f36a35c35cc4f2ef8af68ee2a3eef65e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60969
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-05 08:45:01 +00:00
Yu-hsin Wang
c1b709e46d fastmodel: handling amba control signals
Change-Id: I7a62bdd4bfdb2bba4f7e186b049491b48782d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-04 02:59:58 +00:00
Yu-hsin Wang
b07af1076c systemc: add control extension conversion step
The conversion step will map the control signal in gem5 packet and TLM2
extension.

Change-Id: Ieafb3856723e198d3538a98930e235ed4efbc117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59651
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-07-04 02:59:55 +00:00
Wende Tan
527b91a0e8 configs: Fix timebase-frequency of RISC-V board
Fix the timebase-frequency in the device tree of RISC-V board to make it
consistent with RiscvRTC.

Fixes: 23afee2d9e ("configs: Add RISC-V board to components")
Change-Id: I6fdfba4393ff391185851a036d34bc6ce91eece5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60909
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-02 04:16:07 +00:00
Earl Ou
e54efbd8e9 mem: Use debug trace instead of warn for default backdoor
By default backdoor access fall back to atomic if not
implemented in the ResponsePort. Given this is a common
behavior for most of the IPs, having them print all the
warning creates large number of warning in a big system.

Ideally we want to make this a debug level log, but this
can only be done through the debug trace mechanism.

Change-Id: I8a4074fc58b13c1881ad62897a89774c66880ccb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60790
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-06-29 12:43:11 +00:00
Earl Ou
c0ca47b6ed dev: avoid intpin to reset value at binding stage
By design SimObject should initialize its state at init() stage.
However, the original intpin design will try to reset the sink side when
binding. This could cause unexpected issue as the other side does not
init() yet.

To align with the design, the call to upper()/lower() should be left to
the initiator in the init() function instead of constructor.

Change-Id: Iec8b228715d093381a33e747849119562bd634e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60751
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-06-29 12:42:36 +00:00
Earl Ou
3a65347e0f python: Avoid re-adding child when cloning SimObject
For SimObject type param, we should avoid duplicated addChild
call if it already belongs to other parent.

In the original implementation, the following code:

```

class A(SimObject):
  ...

class B(SimObject):
  a = Param.A(...)

class Top(RealView):
  a = A()
  b = B(a=a)
```

will generate incorrect warning:

```
warn: <orphan B>.a already has parent not resetting parent.
        Note: a is not a parameter of B
	warn: (Previously declared as <orphan Top>.a)
```

The code tries to add `a` as the child of `Top` as well as child of
`Top.b`, which is incorrect.

Change-Id: I8c55c5dd4cc0dd45c68169a2b08450ff053c07aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60789
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-06-29 12:40:28 +00:00