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gpu-compute: Fix for HSA queue remapping

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When a queue is being remapped the write and dispatch
pointers are set to the read pointer. This assumes that
all packets up to the read pointer have been dispatched
and completed.

Change-Id: I4ed0c6c68f16f57c3fb5c3ecba182a43e74078e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61429
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Alexandru Dutu
2022-07-13 07:41:32 -07:00
committed by Alexandru Duțu
parent af9ecf7920
commit 1115f81233
3 changed files with 20 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/dev/hsa/hsa_packet_processor.cc
View File

@@ -618,6 +618,18 @@ AQLRingBuffer::setRdIdx(uint64_t value)
}
}
void
AQLRingBuffer::setWrIdx(uint64_t value)
{
_wrIdx = value;
}
void
AQLRingBuffer::setDispIdx(uint64_t value)
{
_dispIdx = value;
}
bool
AQLRingBuffer::freeEntry(void *pkt)
{

2
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -235,6 +235,8 @@ class AQLRingBuffer
void incDispIdx(uint64_t value) { _dispIdx += value; }
uint64_t compltnPending() { return (_dispIdx - _rdIdx); }
void setRdIdx(uint64_t value);
void setWrIdx(uint64_t value);
void setDispIdx(uint64_t value);
};
struct QCntxt

8
src/dev/hsa/hw_scheduler.cc
View File

@@ -116,6 +116,8 @@ HWScheduler::registerNewQueue(uint64_t hostReadIndexPointer,
new AQLRingBuffer(NUM_DMA_BUFS, hsaPP->name());
if (rd_idx > 0) {
aql_buf->setRdIdx(rd_idx);
aql_buf->setWrIdx(rd_idx);
aql_buf->setDispIdx(rd_idx);
}
DPRINTF(HSAPacketProcessor, "Setting read index for %#lx to %ld\n",
offset, rd_idx);
@@ -340,8 +342,9 @@ HWScheduler::write(Addr db_addr, uint64_t doorbell_reg)
// processor gets commands from host, the correct entry is read after
// remapping.
activeList[al_idx].qDesc->readIndex = doorbell_reg - 1;
DPRINTF(HSAPacketProcessor, "queue %d qDesc->writeIndex %d\n",
al_idx, activeList[al_idx].qDesc->writeIndex);
DPRINTF(HSAPacketProcessor, "q %d readIndex %d writeIndex %d\n",
al_idx, activeList[al_idx].qDesc->readIndex,
activeList[al_idx].qDesc->writeIndex);
// If this queue is mapped, then start DMA to fetch the
// AQL packet
if (regdListMap.find(al_idx) != regdListMap.end()) {
@@ -354,6 +357,7 @@ HWScheduler::unregisterQueue(uint64_t queue_id, int doorbellSize)
{
assert(qidMap.count(queue_id));
Addr db_offset = qidMap[queue_id];
qidMap.erase(queue_id);
auto dbmap_iter = dbMap.find(db_offset);
if (dbmap_iter == dbMap.end()) {
panic("Destroying a non-existing queue (db_offset %x)",