From 1115f812331106085f50c8ae7078a05df494af40 Mon Sep 17 00:00:00 2001 From: Alexandru Dutu Date: Wed, 13 Jul 2022 07:41:32 -0700 Subject: [PATCH] gpu-compute: Fix for HSA queue remapping When a queue is being remapped the write and dispatch pointers are set to the read pointer. This assumes that all packets up to the read pointer have been dispatched and completed. Change-Id: I4ed0c6c68f16f57c3fb5c3ecba182a43e74078e2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61429 Reviewed-by: Matt Sinclair Reviewed-by: Matthew Poremba Maintainer: Matthew Poremba Tested-by: kokoro --- src/dev/hsa/hsa_packet_processor.cc | 12 ++++++++++++ src/dev/hsa/hsa_packet_processor.hh | 2 ++ src/dev/hsa/hw_scheduler.cc | 8 ++++++-- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/dev/hsa/hsa_packet_processor.cc b/src/dev/hsa/hsa_packet_processor.cc index 1236256f71..518dd9c732 100644 --- a/src/dev/hsa/hsa_packet_processor.cc +++ b/src/dev/hsa/hsa_packet_processor.cc @@ -618,6 +618,18 @@ AQLRingBuffer::setRdIdx(uint64_t value) } } +void +AQLRingBuffer::setWrIdx(uint64_t value) +{ + _wrIdx = value; +} + +void +AQLRingBuffer::setDispIdx(uint64_t value) +{ + _dispIdx = value; +} + bool AQLRingBuffer::freeEntry(void *pkt) { diff --git a/src/dev/hsa/hsa_packet_processor.hh b/src/dev/hsa/hsa_packet_processor.hh index 65d1b44a25..b72092538d 100644 --- a/src/dev/hsa/hsa_packet_processor.hh +++ b/src/dev/hsa/hsa_packet_processor.hh @@ -235,6 +235,8 @@ class AQLRingBuffer void incDispIdx(uint64_t value) { _dispIdx += value; } uint64_t compltnPending() { return (_dispIdx - _rdIdx); } void setRdIdx(uint64_t value); + void setWrIdx(uint64_t value); + void setDispIdx(uint64_t value); }; struct QCntxt diff --git a/src/dev/hsa/hw_scheduler.cc b/src/dev/hsa/hw_scheduler.cc index a0f1e87a25..5dfe19110f 100644 --- a/src/dev/hsa/hw_scheduler.cc +++ b/src/dev/hsa/hw_scheduler.cc @@ -116,6 +116,8 @@ HWScheduler::registerNewQueue(uint64_t hostReadIndexPointer, new AQLRingBuffer(NUM_DMA_BUFS, hsaPP->name()); if (rd_idx > 0) { aql_buf->setRdIdx(rd_idx); + aql_buf->setWrIdx(rd_idx); + aql_buf->setDispIdx(rd_idx); } DPRINTF(HSAPacketProcessor, "Setting read index for %#lx to %ld\n", offset, rd_idx); @@ -340,8 +342,9 @@ HWScheduler::write(Addr db_addr, uint64_t doorbell_reg) // processor gets commands from host, the correct entry is read after // remapping. activeList[al_idx].qDesc->readIndex = doorbell_reg - 1; - DPRINTF(HSAPacketProcessor, "queue %d qDesc->writeIndex %d\n", - al_idx, activeList[al_idx].qDesc->writeIndex); + DPRINTF(HSAPacketProcessor, "q %d readIndex %d writeIndex %d\n", + al_idx, activeList[al_idx].qDesc->readIndex, + activeList[al_idx].qDesc->writeIndex); // If this queue is mapped, then start DMA to fetch the // AQL packet if (regdListMap.find(al_idx) != regdListMap.end()) { @@ -354,6 +357,7 @@ HWScheduler::unregisterQueue(uint64_t queue_id, int doorbellSize) { assert(qidMap.count(queue_id)); Addr db_offset = qidMap[queue_id]; + qidMap.erase(queue_id); auto dbmap_iter = dbMap.find(db_offset); if (dbmap_iter == dbMap.end()) { panic("Destroying a non-existing queue (db_offset %x)",