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configs: Fix timebase-frequency of RISC-V board

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Fix the timebase-frequency in the device tree of RISC-V board to make it
consistent with RiscvRTC.

Fixes: 23afee2d9e ("configs: Add RISC-V board to components")
Change-Id: I6fdfba4393ff391185851a036d34bc6ce91eece5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60909
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Wende Tan
2022-07-02 03:22:50 +08:00
committed by Wende Tan
parent eb85b173dd
commit 527b91a0e8
1 changed files with 1 additions and 1 deletions
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src/python/gem5/components/boards/riscv_board.py
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@@ -263,7 +263,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
cpus_node.append(cpus_state.sizeCellsProperty())
# Used by the CLINT driver to set the timer frequency. Value taken from
# RISC-V kernel docs (Note: freedom-u540 is actually 1MHz)
cpus_node.append(FdtPropertyWords("timebase-frequency", [10000000]))
cpus_node.append(FdtPropertyWords("timebase-frequency", [100000000]))
for i, core in enumerate(self.get_processor().get_cores()):
node = FdtNode(f"cpu@{i}")