Files
gem5/src/arch/arm
Giacomo Travaglini 37b6824c4c arch-arm: Fix disassembly for NZCV read/writes
At the moment the instruction is disassembled as an integer
operation:

msrNZCV   x547, x0

Instead of

msr nzcv x0

Change-Id: I3f6576dccbe86db401c73747750ca3cfdf4055d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-22 16:33:58 +01:00
..
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