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arch-arm: Fix disassembly for NZCV read/writes

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At the moment the instruction is disassembled as an integer
operation:

msrNZCV   x547, x0

Instead of

msr nzcv x0

Change-Id: I3f6576dccbe86db401c73747750ca3cfdf4055d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-04-18 15:51:06 +01:00
parent f5a255c68d
commit 37b6824c4c
1 changed files with 15 additions and 5 deletions
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20
src/arch/arm/isa/insts/data64.isa
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@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2013, 2016-2022 Arm Limited
// Copyright (c) 2011-2013, 2016-2023 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -335,13 +335,18 @@ let {{
decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
exec_output += BasicExecute.subst(mrsIop)
buildDataXRegInst("mrsNZCV", 1, '''
mrsNZCVCode = '''
CPSR cpsr = 0;
cpsr.nz = CondCodesNZ;
cpsr.c = CondCodesC;
cpsr.v = CondCodesV;
XDest = cpsr;
''')
'''
mrsNZCViop = ArmInstObjParams("mrs", "MrsNZCV64",
"RegMiscRegImmOp64", mrsNZCVCode)
header_output += RegMiscRegOp64Declare.subst(mrsNZCViop)
decoder_output += RegMiscRegOp64Constructor.subst(mrsNZCViop)
exec_output += BasicExecute.subst(mrsNZCViop)
msrCode = msr_check_code + '''
MiscDest_ud = XOp1;
@@ -382,12 +387,17 @@ let {{
exec_output += DvmInitiateAcc.subst(msrTlbiSIop)
exec_output += DvmCompleteAcc.subst(msrTlbiSIop)
buildDataXRegInst("msrNZCV", 1, '''
msrNZCVCode = '''
CPSR cpsr = XOp1;
CondCodesNZ = cpsr.nz;
CondCodesC = cpsr.c;
CondCodesV = cpsr.v;
''')
'''
msrNZCVIop = ArmInstObjParams("msr", "MsrNZCV64", "MiscRegRegImmOp64",
msrNZCVCode)
header_output += MiscRegRegOp64Declare.subst(msrNZCVIop)
decoder_output += MiscRegRegOp64Constructor.subst(msrNZCVIop)
exec_output += BasicExecute.subst(msrNZCVIop)
msrdczva_ea_code = msr_check_code