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misc: Replace namespace Trace with lowercase trace

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This is what the coding style demands

Change-Id: Ida6a71ad9c2c02cccd584bbaf37a6da751c5b856
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63891
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Giacomo Travaglini
2022-09-28 16:01:17 +01:00
parent 2f1d67f8fe
commit 336e732d54
140 changed files with 809 additions and 809 deletions
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2
src/arch/arm/ArmNativeTrace.py
View File

@@ -31,7 +31,7 @@ from m5.objects.CPUTracers import NativeTrace
class ArmNativeTrace(NativeTrace):
type = "ArmNativeTrace"
cxx_class = "gem5::Trace::ArmNativeTrace"
cxx_class = "gem5::trace::ArmNativeTrace"
cxx_header = "arch/arm/nativetrace.hh"
stop_on_pc_error = Param.Bool(
True, "Stop M5 if it and statetrace's pcs are different"

4
src/arch/arm/insts/misc.cc
View File

@@ -361,7 +361,7 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
}
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
McrMrcMiscInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
@@ -380,7 +380,7 @@ McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
{}
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
McrMrcImplDefined::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
if (fault != NoFault) {

4
src/arch/arm/insts/misc.hh
View File

@@ -414,7 +414,7 @@ class McrMrcMiscInst : public ArmISA::ArmStaticInst
uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -432,7 +432,7 @@ class McrMrcImplDefined : public McrMrcMiscInst
uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;

2
src/arch/arm/insts/misc64.cc
View File

@@ -190,7 +190,7 @@ RegMiscRegImmOp64::iss() const
Fault
MiscRegImplDefined64::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
auto tc = xc->tcBase();
const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);

2
src/arch/arm/insts/misc64.hh
View File

@@ -226,7 +226,7 @@ class MiscRegImplDefined64 : public MiscRegOp64
protected:
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;

2
src/arch/arm/insts/pred_inst.hh
View File

@@ -371,7 +371,7 @@ class PredMacroOp : public PredOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
}

10
src/arch/arm/insts/pseudo.cc
View File

@@ -58,7 +58,7 @@ DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
}
Fault
DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
DecoderFaultInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
const Addr pc = xc->pcState().instAddr();
@@ -130,7 +130,7 @@ FailUnimplemented::FailUnimplemented(const char *_mnemonic,
}
Fault
FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
FailUnimplemented::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
}
@@ -166,7 +166,7 @@ WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
}
Fault
WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
WarnUnimplemented::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n",
@@ -190,7 +190,7 @@ IllegalExecInst::IllegalExecInst(ExtMachInst _machInst)
{}
Fault
IllegalExecInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
IllegalExecInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<IllegalInstSetStateFault>();
}
@@ -200,7 +200,7 @@ DebugStep::DebugStep(ExtMachInst _machInst)
{ }
Fault
DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
DebugStep::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
PCState pc_state = xc->pcState().as<PCState>();
pc_state.debugStep(false);

10
src/arch/arm/insts/pseudo.hh
View File

@@ -57,7 +57,7 @@ class DecoderFaultInst : public ArmISA::ArmStaticInst
DecoderFaultInst(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -83,7 +83,7 @@ class FailUnimplemented : public ArmISA::ArmStaticInst
const std::string& _fullMnemonic);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -113,7 +113,7 @@ class WarnUnimplemented : public ArmISA::ArmStaticInst
const std::string& _fullMnemonic);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -132,7 +132,7 @@ class IllegalExecInst : public ArmISA::ArmStaticInst
IllegalExecInst(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
};
class DebugStep : public ArmISA::ArmStaticInst
@@ -141,7 +141,7 @@ class DebugStep : public ArmISA::ArmStaticInst
DebugStep(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const override;
trace::InstRecord *traceData) const override;
};
} // namespace gem5

12
src/arch/arm/insts/sve_macromem.hh
View File

@@ -89,7 +89,7 @@ class SveLdStructSS : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -162,7 +162,7 @@ class SveStStructSS : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -235,7 +235,7 @@ class SveLdStructSI : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -309,7 +309,7 @@ class SveStStructSI : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -409,7 +409,7 @@ class SveIndexedMemVI : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -514,7 +514,7 @@ class SveIndexedMemSV : public PredMacroOp
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;

12
src/arch/arm/insts/tme64.cc
View File

@@ -89,14 +89,14 @@ MicroTfence64::MicroTfence64(ExtMachInst machInst)
Fault
MicroTfence64::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
Fault
MicroTfence64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("tfence should not have memory semantics");
@@ -105,7 +105,7 @@ MicroTfence64::initiateAcc(ExecContext *xc,
Fault
MicroTfence64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("tfence should not have memory semantics");
@@ -134,7 +134,7 @@ Tstart64::Tstart64(ExtMachInst machInst, RegIndex _dest)
Fault
Tstart64::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");
@@ -171,7 +171,7 @@ Tcancel64::Tcancel64(ExtMachInst machInst, uint64_t _imm)
Fault
Tcancel64::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");
@@ -201,7 +201,7 @@ MicroTcommit64::MicroTcommit64(ExtMachInst machInst)
}
Fault
MicroTcommit64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
MicroTcommit64::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");

26
src/arch/arm/insts/tme64.hh
View File

@@ -106,9 +106,9 @@ class Tstart64 : public TmeRegNone64
public:
Tstart64(ArmISA::ExtMachInst, RegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class Ttest64 : public TmeRegNone64
@@ -119,7 +119,7 @@ class Ttest64 : public TmeRegNone64
public:
Ttest64(ArmISA::ExtMachInst, RegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
};
class Tcancel64 : public TmeImmOp64
@@ -127,9 +127,9 @@ class Tcancel64 : public TmeImmOp64
public:
Tcancel64(ArmISA::ExtMachInst, uint64_t);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class MicroTfence64 : public MicroTmeBasic64
@@ -137,9 +137,9 @@ class MicroTfence64 : public MicroTmeBasic64
public:
MicroTfence64(ArmISA::ExtMachInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class MicroTcommit64 : public MicroTmeBasic64
@@ -147,9 +147,9 @@ class MicroTcommit64 : public MicroTmeBasic64
public:
MicroTcommit64(ArmISA::ExtMachInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};

14
src/arch/arm/insts/tme64classic.cc
View File

@@ -47,7 +47,7 @@ namespace ArmISAInst {
Fault
Tstart64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -56,7 +56,7 @@ Tstart64::initiateAcc(ExecContext *xc,
Fault
Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -65,7 +65,7 @@ Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
Fault
Ttest64::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -74,7 +74,7 @@ Ttest64::execute(
Fault
Tcancel64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -83,7 +83,7 @@ Tcancel64::initiateAcc(ExecContext *xc,
Fault
Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -92,7 +92,7 @@ Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
Fault
MicroTcommit64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -101,7 +101,7 @@ MicroTcommit64::initiateAcc(ExecContext *xc,
Fault
MicroTcommit64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,

14
src/arch/arm/insts/tme64ruby.cc
View File

@@ -52,7 +52,7 @@ namespace ArmISAInst {
Fault
Tstart64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
const uint64_t htm_depth = xc->getHtmTransactionalDepth();
@@ -85,7 +85,7 @@ Tstart64::initiateAcc(ExecContext *xc,
Fault
Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;
@@ -133,7 +133,7 @@ Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
}
Fault
Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
Ttest64::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Dest64 = 0;
@@ -163,7 +163,7 @@ Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
}
Fault
Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Tcancel64::initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -182,7 +182,7 @@ Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Fault
Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;
@@ -209,7 +209,7 @@ Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
Fault
MicroTcommit64::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
const uint64_t htm_depth = xc->getHtmTransactionalDepth();
@@ -238,7 +238,7 @@ MicroTcommit64::initiateAcc(ExecContext *xc,
Fault
MicroTcommit64::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;

4
src/arch/arm/isa/templates/basic.isa
View File

@@ -51,7 +51,7 @@ def template BasicDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -84,7 +84,7 @@ def template BasicConstructor64 {{
def template BasicExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

12
src/arch/arm/isa/templates/branch.isa
View File

@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
@@ -82,7 +82,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -115,10 +115,10 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -149,7 +149,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;

12
src/arch/arm/isa/templates/branch64.isa
View File

@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -67,7 +67,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -90,7 +90,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -112,7 +112,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -135,7 +135,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

2
src/arch/arm/isa/templates/crypto.isa
View File

@@ -39,7 +39,7 @@
// storage/extraction here is fixed as constants.
def template CryptoPredOpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

20
src/arch/arm/isa/templates/data64.isa
View File

@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -100,7 +100,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
ArmExtendType _extendType, int32_t _shiftAmt);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -126,7 +126,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -150,7 +150,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -175,7 +175,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -201,7 +201,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _op3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -227,7 +227,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -253,7 +253,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
RegIndex _op2, ConditionCode _condCode, uint8_t _defCc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -280,7 +280,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

42
src/arch/arm/isa/templates/macromem.isa
View File

@@ -53,10 +53,10 @@ def template MicroMemDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, bool _up,
uint8_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -90,10 +90,10 @@ def template MicroMemPairDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
bool _up, uint8_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -145,10 +145,10 @@ def template MicroNeonMemDeclare {{
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -169,7 +169,7 @@ def template MicroSetPCCPSRDeclare {{
RegIndex _ura,
RegIndex _urb,
RegIndex _urc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -202,19 +202,19 @@ def template MicroSetPCCPSRConstructor {{
def template MicroNeonMemExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::initiateAcc(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
def template MicroNeonExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
////////////////////////////////////////////////////////////////////
@@ -244,14 +244,14 @@ def template MicroNeonMixDeclare {{
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroNeonMixExecute {{
template <class Element>
Fault %(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -299,7 +299,7 @@ def template MicroNeonMixLaneDeclare {{
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -317,7 +317,7 @@ def template MicroIntMovDeclare {{
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroIntMovConstructor {{
@@ -352,7 +352,7 @@ def template MicroIntImmDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb,
int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -397,7 +397,7 @@ def template MicroIntRegDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
int32_t _shiftAmt, ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -423,7 +423,7 @@ def template MicroIntXERegDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
ArmExtendType _type, uint32_t _shiftAmt);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

114
src/arch/arm/isa/templates/mem.isa
View File

@@ -42,7 +42,7 @@
def template PanicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("Execute function executed when it shouldn't be!\n");
return NoFault;
@@ -52,7 +52,7 @@ def template PanicExecute {{
def template PanicInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("InitiateAcc function executed when it shouldn't be!\n");
return NoFault;
@@ -62,7 +62,7 @@ def template PanicInitiateAcc {{
def template PanicCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("CompleteAcc function executed when it shouldn't be!\n");
return NoFault;
@@ -73,7 +73,7 @@ def template PanicCompleteAcc {{
def template SwapExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -109,7 +109,7 @@ def template SwapExecute {{
def template SwapInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -137,7 +137,7 @@ def template SwapInitiateAcc {{
def template SwapCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -163,7 +163,7 @@ def template SwapCompleteAcc {{
def template LoadExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -194,7 +194,7 @@ def template NeonLoadExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -230,7 +230,7 @@ def template NeonLoadExecute {{
def template StoreExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -264,7 +264,7 @@ def template NeonStoreExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -303,7 +303,7 @@ def template NeonStoreExecute {{
def template StoreExExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -342,7 +342,7 @@ def template StoreExExecute {{
def template StoreExInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -371,7 +371,7 @@ def template StoreExInitiateAcc {{
def template StoreInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -401,7 +401,7 @@ def template NeonStoreInitiateAcc {{
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -434,7 +434,7 @@ def template NeonStoreInitiateAcc {{
def template LoadInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -460,7 +460,7 @@ def template NeonLoadInitiateAcc {{
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -487,7 +487,7 @@ def template NeonLoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -515,7 +515,7 @@ def template NeonLoadCompleteAcc {{
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(
PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -543,7 +543,7 @@ def template NeonLoadCompleteAcc {{
def template StoreCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -553,7 +553,7 @@ def template NeonStoreCompleteAcc {{
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(
PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -562,7 +562,7 @@ def template NeonStoreCompleteAcc {{
def template StoreExCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -596,10 +596,10 @@ def template RfeDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -617,10 +617,10 @@ def template SrsDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _regMode, int _mode, bool _wb);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -638,10 +638,10 @@ def template SwapDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -660,10 +660,10 @@ def template LoadStoreDImmDeclare {{
uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -682,10 +682,10 @@ def template StoreExDImmDeclare {{
uint32_t _result, uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -703,10 +703,10 @@ def template LoadStoreImmDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -731,10 +731,10 @@ def template StoreExImmDeclare {{
uint32_t _result, uint32_t _dest, uint32_t _base,
bool _add, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -755,10 +755,10 @@ def template StoreDRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -778,10 +778,10 @@ def template StoreRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -808,10 +808,10 @@ def template LoadDRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -831,10 +831,10 @@ def template LoadRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -858,10 +858,10 @@ def template LoadImmDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override

108
src/arch/arm/isa/templates/mem64.isa
View File

@@ -47,7 +47,7 @@ let {{
def template Load64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -72,7 +72,7 @@ def template Load64Execute {{
def template Load64FpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -97,7 +97,7 @@ def template Load64FpExecute {{
def template Store64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -126,7 +126,7 @@ def template Store64Execute {{
def template Store64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -151,7 +151,7 @@ def template Store64InitiateAcc {{
def template StoreEx64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -185,7 +185,7 @@ def template StoreEx64Execute {{
def template StoreEx64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -210,7 +210,7 @@ def template StoreEx64InitiateAcc {{
def template Load64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -230,7 +230,7 @@ def template Load64InitiateAcc {{
def template Load64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -255,7 +255,7 @@ def template Load64CompleteAcc {{
def template Store64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -264,7 +264,7 @@ def template Store64CompleteAcc {{
def template StoreEx64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -293,10 +293,10 @@ def template DCStore64Declare {{
%(class_name)s(ExtMachInst machInst, RegIndex _base,
MiscRegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -321,7 +321,7 @@ def template DCStore64Constructor {{
def template DCStore64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -352,7 +352,7 @@ def template DCStore64Execute {{
def template DCStore64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -387,10 +387,10 @@ def template LoadStoreImm64Declare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _base, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -413,10 +413,10 @@ def template LoadStoreImmU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -439,10 +439,10 @@ def template LoadStoreImmDU64Declare {{
int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
bool acrel = false);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -467,10 +467,10 @@ def template StoreImmDEx64Declare {{
RegIndex _result, RegIndex _dest, RegIndex _dest2,
RegIndex _base, int64_t _imm = 0);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -487,10 +487,10 @@ def template LoadStoreReg64Declare {{
RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -514,10 +514,10 @@ def template LoadStoreRegU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -538,10 +538,10 @@ def template LoadStoreRaw64Declare {{
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -562,10 +562,10 @@ def template LoadStoreEx64Declare {{
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -585,10 +585,10 @@ def template LoadStoreLit64Declare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst, RegIndex _dest, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -610,10 +610,10 @@ def template LoadStoreLitU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -782,7 +782,7 @@ def template LoadStoreLitU64Constructor {{
def template AmoOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -812,7 +812,7 @@ def template AmoOpExecute {{
def template AmoOpInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -834,7 +834,7 @@ def template AmoOpInitiateAcc {{
def template AmoOpCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -862,10 +862,10 @@ def template AmoOpDeclare {{
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -901,10 +901,10 @@ def template AmoArithmeticOpDeclare {{
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override

52
src/arch/arm/isa/templates/misc.isa
View File

@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -76,7 +76,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint8_t _sysM, bool _r);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint8_t _sysM, bool _r);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -138,7 +138,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, uint8_t mask);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -166,7 +166,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -195,7 +195,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
RegIndex _dest, RegIndex _dest2, uint32_t imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -226,7 +226,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2,
MiscRegIndex _dest, uint32_t imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -256,7 +256,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -283,7 +283,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -311,7 +311,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -340,7 +340,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -371,7 +371,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _op3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -402,7 +402,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -432,7 +432,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -462,7 +462,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, RegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -492,7 +492,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, MiscRegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -522,7 +522,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -552,7 +552,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -583,7 +583,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -614,7 +614,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm,
RegIndex _op1, int32_t _shiftAmt,
ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -646,17 +646,17 @@ def template MiscRegRegImmMemOpDeclare {{
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
def template Mcr15Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -687,7 +687,7 @@ def template Mcr15Execute {{
def template Mcr15InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -718,7 +718,7 @@ def template Mcr15InitiateAcc {{
def template Mcr15CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}

32
src/arch/arm/isa/templates/misc64.isa
View File

@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -69,7 +69,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -95,7 +95,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -121,7 +121,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -146,7 +146,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -172,7 +172,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
MiscRegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -197,7 +197,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -221,7 +221,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const;
};
}};
@@ -246,10 +246,10 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1, bool dvm_enabled);
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
Fault execute(ExecContext *, Trace::InstRecord *) const override;
trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -266,10 +266,10 @@ def template DvmDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, bool dvm_enabled);
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
Fault execute(ExecContext *, Trace::InstRecord *) const override;
trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -306,7 +306,7 @@ def template DvmConstructor {{
def template DvmInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -326,7 +326,7 @@ def template DvmInitiateAcc {{
def template DvmCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}

4
src/arch/arm/isa/templates/mult.isa
View File

@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _reg0,
RegIndex _reg1, RegIndex _reg2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -76,7 +76,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _reg0, RegIndex _reg1,
RegIndex _reg2, RegIndex _reg3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

16
src/arch/arm/isa/templates/neon.isa
View File

@@ -74,7 +74,7 @@ class %(class_name)s : public %(base_class)s
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -135,7 +135,7 @@ class %(class_name)s : public %(base_class)s
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -193,14 +193,14 @@ class %(class_name)s : public %(base_class)s
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template NeonExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
output header {{
@@ -233,7 +233,7 @@ def template NeonEqualRegExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -285,7 +285,7 @@ def template NeonUnequalRegExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
typedef typename bigger_type_t<Element>::type BigElement;
Fault fault = NoFault;

42
src/arch/arm/isa/templates/neon64.isa
View File

@@ -60,7 +60,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -86,7 +86,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -134,7 +134,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -183,21 +183,21 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template NeonXExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
def template NeonXEqualRegOpExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -232,7 +232,7 @@ def template NeonXUnequalRegOpExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
typedef typename bigger_type_t<Element>::type BigElement;
Fault fault = NoFault;
@@ -299,17 +299,17 @@ def template MicroNeonMemDeclare64 {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
def template NeonLoadExecute64 {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -340,7 +340,7 @@ def template NeonLoadExecute64 {{
def template NeonLoadInitiateAcc64 {{
Fault
%(class_name)s::initiateAcc(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -362,7 +362,7 @@ def template NeonLoadInitiateAcc64 {{
def template NeonLoadCompleteAcc64 {{
Fault
%(class_name)s::completeAcc(
PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -388,7 +388,7 @@ def template NeonLoadCompleteAcc64 {{
def template NeonStoreExecute64 {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -422,7 +422,7 @@ def template NeonStoreExecute64 {{
def template NeonStoreInitiateAcc64 {{
Fault
%(class_name)s::initiateAcc(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -450,7 +450,7 @@ def template NeonStoreInitiateAcc64 {{
def template NeonStoreCompleteAcc64 {{
Fault
%(class_name)s::completeAcc(
PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -533,7 +533,7 @@ def template MicroNeonMixDeclare64 {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -556,14 +556,14 @@ def template MicroNeonMixLaneDeclare64 {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroNeonMixExecute64 {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;

12
src/arch/arm/isa/templates/pred.isa
View File

@@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, uint32_t _imm, bool _rotC=true);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -146,7 +146,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _shift,
ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -171,7 +171,7 @@ def template DataRegRegConstructor {{
def template PredOpExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -195,7 +195,7 @@ def template PredOpExecute {{
def template QuiescePredOpExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -221,7 +221,7 @@ def template QuiescePredOpExecute {{
def template QuiescePredOpExecuteWithFixup {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;

98
src/arch/arm/isa/templates/sve.isa
View File

@@ -69,7 +69,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -95,7 +95,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -144,7 +144,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -168,7 +168,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -195,7 +195,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -221,7 +221,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -247,7 +247,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -273,7 +273,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -300,7 +300,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -326,7 +326,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -379,7 +379,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -405,7 +405,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -431,7 +431,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -457,7 +457,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -483,7 +483,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -509,7 +509,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -535,7 +535,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -564,7 +564,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -590,7 +590,7 @@ class SveIndexII : public SveIndexIIOp
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -616,7 +616,7 @@ class SveIndexIR : public SveIndexIROp
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -642,7 +642,7 @@ class SveIndexRI : public SveIndexRIOp
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -668,7 +668,7 @@ class SveIndexRR : public SveIndexRROp
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -692,7 +692,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -717,7 +717,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -742,7 +742,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -769,7 +769,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -794,7 +794,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -817,7 +817,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -842,7 +842,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -868,7 +868,7 @@ class %(class_name)s : public %(base_class)s
esize = sizeof(Element);
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -888,7 +888,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -910,7 +910,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -936,7 +936,7 @@ class %(class_name)s : public %(base_class)s
scalar_width = (sizeof(Element) == 8) ? 64 : 32;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -962,7 +962,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -980,7 +980,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -998,7 +998,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1016,7 +1016,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1034,7 +1034,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1052,7 +1052,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1081,7 +1081,7 @@ class %(class_name)s : public %(base_class)s
esize = sizeof(Element);
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1110,7 +1110,7 @@ class %(class_name)s : public %(base_class)s
esize = sizeof(Element);
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1137,7 +1137,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1164,7 +1164,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1172,7 +1172,7 @@ def template SveWideningOpExecute {{
template <class SElement, class DElement>
Fault
%(class_name)s<SElement, DElement>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1190,7 +1190,7 @@ def template SveWideningOpExecute {{
def template SveNonTemplatedOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1209,7 +1209,7 @@ def template SveOpExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1227,5 +1227,5 @@ def template SveOpExecute {{
def template SveOpExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};

112
src/arch/arm/isa/templates/sve_mem.isa
View File

@@ -54,10 +54,10 @@ def template SveMemFillSpillOpDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -88,10 +88,10 @@ def template SveContigMemSSOpDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -122,10 +122,10 @@ def template SveContigMemSIOpDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -138,22 +138,22 @@ def template SveContigMemSIOpDeclare {{
def template SveContigMemExecDeclare {{
template
Fault %(class_name)s%(tpl_args)s::execute(ExecContext *,
Trace::InstRecord *) const;
trace::InstRecord *) const;
template
Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *,
Trace::InstRecord *) const;
trace::InstRecord *) const;
template
Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr,
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
def template SveContigLoadExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -188,7 +188,7 @@ def template SveContigLoadInitiateAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -215,7 +215,7 @@ def template SveContigLoadCompleteAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
unsigned eCount =
@@ -243,7 +243,7 @@ def template SveContigStoreExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -281,7 +281,7 @@ def template SveContigStoreInitiateAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -315,7 +315,7 @@ def template SveContigStoreCompleteAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -325,7 +325,7 @@ def template SveLoadAndReplExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -357,7 +357,7 @@ def template SveLoadAndReplInitiateAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -383,7 +383,7 @@ def template SveLoadAndReplCompleteAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] bool aarch64 = true;
@@ -454,10 +454,10 @@ def template SveIndexedMemVIMicroopDeclare {{
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -542,10 +542,10 @@ def template SveIndexedMemSVMicroopDeclare {{
}
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -581,7 +581,7 @@ def template SveGatherLoadMicroopExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -630,7 +630,7 @@ def template SveGatherLoadMicroopInitiateAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -673,7 +673,7 @@ def template SveGatherLoadMicroopCompleteAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
@@ -698,7 +698,7 @@ def template SveScatterStoreMicroopExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -729,7 +729,7 @@ def template SveScatterStoreMicroopInitiateAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -758,7 +758,7 @@ def template SveScatterStoreMicroopCompleteAcc {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -786,7 +786,7 @@ def template SveFirstFaultWritebackMicroopDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -804,7 +804,7 @@ def template SveFirstFaultWritebackMicroopExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
@@ -847,7 +847,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -864,7 +864,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{
def template SveGatherLoadCpySrcVecMicroopExecute {{
Fault
SveGatherLoadCpySrcVecMicroop::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -916,10 +916,10 @@ def template SveStructMemSIMicroopDeclare {{
baseIsSP = isSP(_base);
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -970,22 +970,22 @@ def template SveStructMemSIMicroopDeclare {{
def template SveStructMemExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(ExecContext *,
Trace::InstRecord *) const;
trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::initiateAcc(ExecContext *,
Trace::InstRecord *) const;
trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
def template SveStructLoadExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1019,7 +1019,7 @@ def template SveStructLoadInitiateAcc {{
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1046,7 +1046,7 @@ def template SveStructLoadCompleteAcc {{
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] bool aarch64 = true;
@@ -1078,7 +1078,7 @@ def template SveStructStoreExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1116,7 +1116,7 @@ def template SveStructStoreInitiateAcc {{
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1150,7 +1150,7 @@ def template SveStructStoreCompleteAcc {{
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -1193,10 +1193,10 @@ def template SveStructMemSSMicroopDeclare {{
baseIsSP = isSP(_base);
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -1271,7 +1271,7 @@ def template SveIntrlvMicroopDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -1312,7 +1312,7 @@ def template SveDeIntrlvMicroopDeclare {{
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -1329,14 +1329,14 @@ def template SveDeIntrlvMicroopDeclare {{
def template SveIntrlvMicroopExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
ExecContext *, Trace::InstRecord *) const;
ExecContext *, trace::InstRecord *) const;
}};
def template SveIntrlvMicroopExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

10
src/arch/arm/isa/templates/vfp.isa
View File

@@ -106,7 +106,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -137,7 +137,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -168,7 +168,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -202,7 +202,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1, RegIndex _op2,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -237,7 +237,7 @@ class %(class_name)s : public %(base_class)s
RegIndex _dest, RegIndex _op1, RegIndex _op2,
ConditionCode _cond,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

2
src/arch/arm/isa/templates/vfp64.isa
View File

@@ -93,7 +93,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1, RegIndex _op2,
RegIndex _op3, VfpMicroMode mode=VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

10
src/arch/arm/nativetrace.cc
View File

@@ -55,7 +55,7 @@ namespace gem5
using namespace ArmISA;
namespace Trace {
namespace trace {
[[maybe_unused]] static const char *regNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -68,7 +68,7 @@ namespace Trace {
};
void
Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
ArmNativeTrace::ThreadState::update(NativeTrace *parent)
{
oldState = state[current];
current = (current + 1) % 2;
@@ -103,7 +103,7 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
}
void
Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
ArmNativeTrace::ThreadState::update(ThreadContext *tc)
{
oldState = state[current];
current = (current + 1) % 2;
@@ -141,7 +141,7 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
}
void
Trace::ArmNativeTrace::check(NativeTraceRecord *record)
ArmNativeTrace::check(NativeTraceRecord *record)
{
ThreadContext *tc = record->getThread();
// This area is read only on the target. It can't stop there to tell us
@@ -223,5 +223,5 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
}
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/nativetrace.hh
View File

@@ -36,7 +36,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
class ArmNativeTrace : public NativeTrace
{
@@ -110,7 +110,7 @@ class ArmNativeTrace : public NativeTrace
void check(NativeTraceRecord *record);
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_NATIVETRACE_HH__

4
src/arch/arm/tracers/TarmacTrace.py
View File

@@ -40,7 +40,7 @@ from m5.objects.InstTracer import InstTracer
class TarmacParser(InstTracer):
type = "TarmacParser"
cxx_class = "gem5::Trace::TarmacParser"
cxx_class = "gem5::trace::TarmacParser"
cxx_header = "arch/arm/tracers/tarmac_parser.hh"
path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
@@ -69,7 +69,7 @@ class TarmacParser(InstTracer):
class TarmacTracer(InstTracer):
type = "TarmacTracer"
cxx_class = "gem5::Trace::TarmacTracer"
cxx_class = "gem5::trace::TarmacTracer"
cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
start_tick = Param.Tick(

4
src/arch/arm/tracers/tarmac_base.cc
View File

@@ -50,7 +50,7 @@ namespace gem5
using namespace ArmISA;
namespace Trace {
namespace trace {
TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
@@ -118,5 +118,5 @@ TarmacBaseRecord::pcToISetState(const PCStateBase &pc)
return isetstate;
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/tracers/tarmac_base.hh
View File

@@ -60,7 +60,7 @@ namespace gem5
class ThreadContext;
namespace Trace {
namespace trace {
class TarmacBaseRecord : public InstRecord
{
@@ -147,7 +147,7 @@ class TarmacBaseRecord : public InstRecord
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__

10
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -64,7 +64,7 @@ namespace gem5
using namespace ArmISA;
namespace Trace {
namespace trace {
// TARMAC Parser static variables
const int TarmacParserRecord::MaxLineLength;
@@ -745,7 +745,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
void
TarmacParserRecord::TarmacParserRecordEvent::process()
{
std::ostream &outs = Trace::output();
std::ostream &outs = trace::output();
std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
end = destRegRecords.end();
@@ -934,7 +934,7 @@ void
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
const PCStateBase &pc)
{
std::ostream &outs = Trace::output();
std::ostream &outs = trace::output();
outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
<< curTick() << " ticks\n"
<< "[seq_num: " << std::dec << instRecord.seq_num
@@ -963,7 +963,7 @@ TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
void
TarmacParserRecord::dump()
{
std::ostream &outs = Trace::output();
std::ostream &outs = trace::output();
uint64_t written_data = 0;
unsigned mem_flags = 3 | ArmISA::MMU::AllowUnaligned;
@@ -1357,5 +1357,5 @@ TarmacParserRecord::iSetStateToStr(ISetState isetstate) const
}
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/tracers/tarmac_parser.hh
View File

@@ -62,7 +62,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
class TarmacParserRecord : public TarmacBaseRecord
{
@@ -300,7 +300,7 @@ class TarmacParser : public InstTracer
bool macroopInProgress;
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__

6
src/arch/arm/tracers/tarmac_record.cc
View File

@@ -47,7 +47,7 @@ namespace gem5
using namespace ArmISA;
namespace Trace {
namespace trace {
// TARMAC Instruction Record static variables
uint64_t TarmacTracerRecord::TraceInstEntry::instCount = 0;
@@ -374,7 +374,7 @@ template<typename Queue>
void
TarmacTracerRecord::flushQueues(Queue& queue)
{
std::ostream &outs = Trace::output();
std::ostream &outs = trace::output();
for (const auto &single_entry : queue) {
single_entry->print(outs);
@@ -446,5 +446,5 @@ TarmacTracerRecord::TraceRegEntry::print(
values[Lo]); /* Register value */
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/tracers/tarmac_record.hh
View File

@@ -54,7 +54,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
class TarmacContext;
@@ -258,7 +258,7 @@ class TarmacTracerRecord : public TarmacBaseRecord
TarmacTracer& tracer;
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__

4
src/arch/arm/tracers/tarmac_record_v8.cc
View File

@@ -48,7 +48,7 @@ namespace gem5
using namespace ArmISA;
namespace Trace {
namespace trace {
TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(
const TarmacContext& tarmCtx,
@@ -313,5 +313,5 @@ TarmacTracerRecordV8::TraceRegEntryV8::formatReg() const
}
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/tracers/tarmac_record_v8.hh
View File

@@ -48,7 +48,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
/**
* TarmacTracer record for ARMv8 CPUs:
@@ -158,7 +158,7 @@ class TarmacTracerRecordV8 : public TarmacTracerRecord
void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr);
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__

4
src/arch/arm/tracers/tarmac_tracer.cc
View File

@@ -45,7 +45,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
std::string
TarmacContext::tarmacCpuName() const
@@ -95,5 +95,5 @@ TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
}
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/arm/tracers/tarmac_tracer.hh
View File

@@ -55,7 +55,7 @@ namespace gem5
class ThreadContext;
namespace Trace {
namespace trace {
/**
* This object type is encapsulating the informations needed by
@@ -129,7 +129,7 @@ class TarmacTracer : public InstTracer
std::vector<RegPtr> regQueue;
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__

34
src/arch/generic/memhelpers.hh
View File

@@ -64,7 +64,7 @@ initiateMemRead(XC *xc, Addr addr, std::size_t size,
/// to determine the size of the access.
template <class XC, class MemT>
Fault
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
initiateMemRead(XC *xc, trace::InstRecord *traceData, Addr addr,
MemT &mem, Request::Flags flags)
{
static const std::vector<bool> byte_enable(sizeof(MemT), true);
@@ -75,7 +75,7 @@ initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
/// Extract the data returned from a timing mode read.
template <ByteOrder Order, class MemT>
void
getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
getMem(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
mem = pkt->get<MemT>(Order);
if (traceData)
@@ -84,14 +84,14 @@ getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
template <class MemT>
void
getMemLE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
getMemLE(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
getMem<ByteOrder::little>(pkt, mem, traceData);
}
template <class MemT>
void
getMemBE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
getMemBE(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
getMem<ByteOrder::big>(pkt, mem, traceData);
}
@@ -109,7 +109,7 @@ readMemAtomic(XC *xc, Addr addr, uint8_t *mem,
/// Read from memory in atomic mode.
template <ByteOrder Order, class XC, class MemT>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
readMemAtomic(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
@@ -126,7 +126,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
template <class XC, class MemT>
Fault
readMemAtomicLE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
readMemAtomicLE(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
return readMemAtomic<ByteOrder::little>(
@@ -135,7 +135,7 @@ readMemAtomicLE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
template <class XC, class MemT>
Fault
readMemAtomicBE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
readMemAtomicBE(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
return readMemAtomic<ByteOrder::big>(xc, traceData, addr, mem, flags);
@@ -153,7 +153,7 @@ writeMemTiming(XC *xc, uint8_t *mem, Addr addr,
template <ByteOrder Order, class XC, class MemT>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
writeMemTiming(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
if (traceData) {
@@ -167,7 +167,7 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
template <class XC, class MemT>
Fault
writeMemTimingLE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
writeMemTimingLE(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
return writeMemTiming<ByteOrder::little>(
@@ -176,7 +176,7 @@ writeMemTimingLE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
template <class XC, class MemT>
Fault
writeMemTimingBE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
writeMemTimingBE(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
return writeMemTiming<ByteOrder::big>(
@@ -195,7 +195,7 @@ writeMemAtomic(XC *xc, uint8_t *mem, Addr addr,
template <ByteOrder Order, class XC, class MemT>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
writeMemAtomic(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
if (traceData) {
@@ -216,7 +216,7 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
template <class XC, class MemT>
Fault
writeMemAtomicLE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
writeMemAtomicLE(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
return writeMemAtomic<ByteOrder::little>(
@@ -225,7 +225,7 @@ writeMemAtomicLE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
template <class XC, class MemT>
Fault
writeMemAtomicBE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
writeMemAtomicBE(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
return writeMemAtomic<ByteOrder::big>(
@@ -235,7 +235,7 @@ writeMemAtomicBE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
/// Do atomic read-modify-write (AMO) in atomic mode
template <ByteOrder Order, class XC, class MemT>
Fault
amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
amoMemAtomic(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
assert(_amo_op);
@@ -257,7 +257,7 @@ amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
template <class XC, class MemT>
Fault
amoMemAtomicLE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
amoMemAtomicLE(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
return amoMemAtomic<ByteOrder::little>(
@@ -266,7 +266,7 @@ amoMemAtomicLE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
template <class XC, class MemT>
Fault
amoMemAtomicBE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
amoMemAtomicBE(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
return amoMemAtomic<ByteOrder::big>(
@@ -276,7 +276,7 @@ amoMemAtomicBE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
/// Do atomic read-modify-wrote (AMO) in timing mode
template <class XC, class MemT>
Fault
initiateMemAMO(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT& mem,
initiateMemAMO(XC *xc, trace::InstRecord *traceData, Addr addr, MemT& mem,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
assert(_amo_op);

4
src/arch/mips/isa/formats/basic.isa
View File

@@ -41,7 +41,7 @@ def template BasicDeclare {{
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -59,7 +59,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

6
src/arch/mips/isa/formats/control.isa
View File

@@ -64,7 +64,7 @@ output header {{
// Basic instruction class execute method template.
def template CP0Execute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -86,7 +86,7 @@ def template CP0Execute {{
def template CP1Execute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -108,7 +108,7 @@ def template CP1Execute {{
// Basic instruction class execute method template.
def template ControlTLBExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

4
src/arch/mips/isa/formats/dsp.isa
View File

@@ -61,7 +61,7 @@ output header {{
// Dsp instruction class execute method template.
def template DspExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -95,7 +95,7 @@ def template DspExecute {{
// DspHiLo instruction class execute method template.
def template DspHiLoExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

6
src/arch/mips/isa/formats/fp.isa
View File

@@ -98,7 +98,7 @@ output exec {{
template <class T>
bool
fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
Trace::InstRecord *traceData)
trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
assert(sizeof(T) == 4);
@@ -119,7 +119,7 @@ output exec {{
template <class T>
bool
fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
Trace::InstRecord *traceData)
trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
T src_op = dest_val;
@@ -162,7 +162,7 @@ output exec {{
def template FloatingPointExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

6
src/arch/mips/isa/formats/int.isa
View File

@@ -109,7 +109,7 @@ output header {{
def template HiLoExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -129,7 +129,7 @@ def template HiLoExecute {{
def template HiLoRsSelExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -153,7 +153,7 @@ def template HiLoRsSelExecute {{
def template HiLoRdSelExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

30
src/arch/mips/isa/formats/mem.isa
View File

@@ -136,10 +136,10 @@ def template LoadStoreDeclare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(Packet *, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -155,7 +155,7 @@ def template LoadStoreConstructor {{
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -187,7 +187,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -213,7 +213,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -243,7 +243,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -277,7 +277,7 @@ def template StoreExecute {{
def template StoreFPExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -312,7 +312,7 @@ def template StoreFPExecute {{
def template StoreCondExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -346,7 +346,7 @@ def template StoreCondExecute {{
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -373,7 +373,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -382,7 +382,7 @@ def template StoreCompleteAcc {{
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -405,7 +405,7 @@ def template StoreCondCompleteAcc {{
def template MiscExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA = 0;
Fault fault = NoFault;
@@ -425,7 +425,7 @@ def template MiscExecute {{
def template MiscInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
return NoFault;
@@ -435,7 +435,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");

4
src/arch/mips/isa/formats/mt.isa
View File

@@ -107,7 +107,7 @@ output exec {{
def template ThreadRegisterExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] int64_t data;
@@ -146,7 +146,7 @@ def template ThreadRegisterExecute {{
def template MTExecute{{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

4
src/arch/mips/isa/formats/noop.isa
View File

@@ -54,7 +54,7 @@ output header {{
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -80,7 +80,7 @@ output decoder {{
output exec {{
Fault
Nop::execute(ExecContext *, Trace::InstRecord *) const
Nop::execute(ExecContext *, trace::InstRecord *) const
{
return NoFault;
}

2
src/arch/mips/isa/formats/tlbop.isa
View File

@@ -56,7 +56,7 @@ output decoder {{
def template TlbOpExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
//Write the resulting state to the execution context
%(op_wb)s;

2
src/arch/mips/isa/formats/trap.isa
View File

@@ -75,7 +75,7 @@ output decoder {{
def template TrapExecute {{
// Edit This Template When Traps Are Implemented
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
//Write the resulting state to the execution context
%(op_wb)s;

20
src/arch/mips/isa/formats/unimp.isa
View File

@@ -51,7 +51,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -68,7 +68,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -85,7 +85,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -102,7 +102,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -133,7 +133,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -179,7 +179,7 @@ output decoder {{
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
@@ -189,7 +189,7 @@ output exec {{
Fault
CP0Unimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
@@ -206,7 +206,7 @@ output exec {{
Fault
CP1Unimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
@@ -223,7 +223,7 @@ output exec {{
Fault
CP2Unimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2))
@@ -240,7 +240,7 @@ output exec {{
Fault
WarnUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n", mnemonic);

4
src/arch/mips/isa/formats/unknown.isa
View File

@@ -49,7 +49,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -68,7 +68,7 @@ output decoder {{
output exec {{
Fault
Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<ReservedInstructionFault>();
}

4
src/arch/power/isa/formats/basic.isa
View File

@@ -39,7 +39,7 @@ def template BasicDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -57,7 +57,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;

18
src/arch/power/isa/formats/mem.isa
View File

@@ -45,10 +45,10 @@ def template LoadStoreDeclare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -65,7 +65,7 @@ def template LoadStoreConstructor {{
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -94,7 +94,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -115,7 +115,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA;
Fault fault = NoFault;
@@ -146,7 +146,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -180,7 +180,7 @@ def template StoreExecute {{
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -209,7 +209,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA;
Fault fault = NoFault;

2
src/arch/power/isa/formats/misc.isa
View File

@@ -33,7 +33,7 @@
def template MiscOpExecute {{
Fault %(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

8
src/arch/power/isa/formats/unimp.isa
View File

@@ -53,7 +53,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -84,7 +84,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -110,7 +110,7 @@ output decoder {{
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, PO,
@@ -120,7 +120,7 @@ output exec {{
Fault
WarnUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n", mnemonic);

4
src/arch/power/isa/formats/unknown.isa
View File

@@ -51,7 +51,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -70,7 +70,7 @@ output decoder {{
output exec {{
Fault
Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
inform("attempt to execute unknown instruction at %s"
"(inst 0x%08x, opcode 0x%x, binary: %s)",

2
src/arch/riscv/insts/amo.cc
View File

@@ -54,7 +54,7 @@ MemFenceMicro::generateDisassembly(
}
Fault MemFenceMicro::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}

2
src/arch/riscv/insts/amo.hh
View File

@@ -52,7 +52,7 @@ class MemFenceMicro : public RiscvMicroInst
protected:
using RiscvMicroInst::RiscvMicroInst;
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};

6
src/arch/riscv/insts/static_inst.hh
View File

@@ -116,20 +116,20 @@ class RiscvMacroInst : public RiscvStaticInst
}
Fault
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const override
trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}

2
src/arch/riscv/insts/unknown.hh
View File

@@ -58,7 +58,7 @@ class Unknown : public RiscvStaticInst
{}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
return std::make_shared<UnknownInstFault>(machInst);
}

30
src/arch/riscv/isa/formats/amo.isa
View File

@@ -59,10 +59,10 @@ def template AtomicMemOpRMWDeclare {{
// Constructor
%(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -91,10 +91,10 @@ def template LRSCMicroDeclare {{
// Constructor
%(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -233,7 +233,7 @@ def template AtomicMemOpRMWConstructor {{
def template LoadReservedExecute {{
Fault
%(class_name)s::%(class_name)sMicro::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
@@ -260,7 +260,7 @@ def template LoadReservedExecute {{
def template StoreCondExecute {{
Fault %(class_name)s::%(class_name)sMicro::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
uint64_t result;
@@ -294,7 +294,7 @@ def template StoreCondExecute {{
def template AtomicMemOpRMWExecute {{
Fault %(class_name)s::%(class_name)sRMW::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -328,7 +328,7 @@ def template AtomicMemOpRMWExecute {{
def template LoadReservedInitiateAcc {{
Fault
%(class_name)s::%(class_name)sMicro::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -346,7 +346,7 @@ def template LoadReservedInitiateAcc {{
def template StoreCondInitiateAcc {{
Fault
%(class_name)s::%(class_name)sMicro::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -374,7 +374,7 @@ def template StoreCondInitiateAcc {{
def template AtomicMemOpRMWInitiateAcc {{
Fault
%(class_name)s::%(class_name)sRMW::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -397,7 +397,7 @@ def template AtomicMemOpRMWInitiateAcc {{
def template LoadReservedCompleteAcc {{
Fault
%(class_name)s::%(class_name)sMicro::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -413,7 +413,7 @@ def template LoadReservedCompleteAcc {{
def template StoreCondCompleteAcc {{
Fault %(class_name)s::%(class_name)sMicro::completeAcc(Packet *pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_dest_decl)s;
@@ -430,7 +430,7 @@ def template StoreCondCompleteAcc {{
def template AtomicMemOpRMWCompleteAcc {{
Fault %(class_name)s::%(class_name)sRMW::completeAcc(Packet *pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;

4
src/arch/riscv/isa/formats/basic.isa
View File

@@ -40,7 +40,7 @@ def template BasicDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
using %(base_class)s::generateDisassembly;
};
}};
@@ -60,7 +60,7 @@ def template BasicConstructor {{
def template BasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;

4
src/arch/riscv/isa/formats/compressed.isa
View File

@@ -126,7 +126,7 @@ def template CBasicDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -136,7 +136,7 @@ def template CBasicDeclare {{
def template CBasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;

2
src/arch/riscv/isa/formats/fp.isa
View File

@@ -34,7 +34,7 @@
//
def template FloatExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)

18
src/arch/riscv/isa/formats/mem.isa
View File

@@ -44,10 +44,10 @@ def template LoadStoreDeclare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
@@ -98,7 +98,7 @@ def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
def template LoadExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
@@ -127,7 +127,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -145,7 +145,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -162,7 +162,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -193,7 +193,7 @@ def template StoreExecute {{
def template StoreInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Addr EA;
@@ -222,7 +222,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}

18
src/arch/riscv/isa/formats/standard.isa
View File

@@ -45,7 +45,7 @@ def template ImmDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const override;
};
@@ -64,7 +64,7 @@ def template ImmConstructor {{
def template ImmExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -90,7 +90,7 @@ def template ImmExecute {{
def template CILuiExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -118,7 +118,7 @@ def template CILuiExecute {{
def template FenceExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -169,7 +169,7 @@ def template BranchDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(
@@ -185,7 +185,7 @@ def template BranchDeclare {{
def template BranchExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -227,7 +227,7 @@ def template JumpDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(
@@ -286,7 +286,7 @@ def template JumpConstructor {{
def template JumpExecute {{
Fault
%(class_name)s::execute(
ExecContext *xc, Trace::InstRecord *traceData) const
ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -321,7 +321,7 @@ def template JumpExecute {{
def template CSRExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
// We assume a riscv instruction is always run with a riscv ISA.
auto isa = static_cast<RiscvISA::ISA*>(xc->tcBase()->getIsaPtr());

2
src/arch/sparc/SparcNativeTrace.py
View File

@@ -32,5 +32,5 @@ from m5.objects.CPUTracers import NativeTrace
class SparcNativeTrace(NativeTrace):
type = "SparcNativeTrace"
cxx_class = "gem5::Trace::SparcNativeTrace"
cxx_class = "gem5::trace::SparcNativeTrace"
cxx_header = "arch/sparc/nativetrace.hh"

6
src/arch/sparc/insts/micro.hh
View File

@@ -71,19 +71,19 @@ class SparcMacroInst : public SparcStaticInst
}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
initiateAcc(ExecContext *, Trace::InstRecord *) const override
initiateAcc(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override
completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}

4
src/arch/sparc/insts/nop.cc
View File

@@ -48,7 +48,7 @@ output header {{
}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const
execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -71,7 +71,7 @@ output decoder {{
def template NopExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
// Nothing to see here, move along
return NoFault;

2
src/arch/sparc/insts/nop.hh
View File

@@ -56,7 +56,7 @@ class Nop : public SparcStaticInst
}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return NoFault;
}

4
src/arch/sparc/insts/unimp.hh
View File

@@ -62,7 +62,7 @@ class FailUnimplemented : public SparcStaticInst
{}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return std::make_shared<GenericISA::M5PanicFault>(
"attempt to execute unimplemented instruction '%s' (inst %#08x)",
@@ -99,7 +99,7 @@ class WarnUnimplemented : public SparcStaticInst
{}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
if (!warned) {
return std::make_shared<GenericISA::M5WarnFault>(

2
src/arch/sparc/insts/unknown.hh
View File

@@ -50,7 +50,7 @@ class Unknown : public SparcStaticInst
{}
Fault
execute(ExecContext *, Trace::InstRecord *) const override
execute(ExecContext *, trace::InstRecord *) const override
{
return std::make_shared<IllegalInstruction>();
}

14
src/arch/sparc/isa/formats/basic.isa
View File

@@ -37,7 +37,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -54,8 +54,8 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
GEM5_NO_INLINE Fault doFpOp(ExecContext *, Trace::InstRecord *) const;
Fault execute(ExecContext *, trace::InstRecord *) const override;
GEM5_NO_INLINE Fault doFpOp(ExecContext *, trace::InstRecord *) const;
};
}};
@@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor.
%(class_name)s(const char *mnemonic, ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -100,7 +100,7 @@ def template BasicConstructorWithMnemonic {{
def template BasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -119,7 +119,7 @@ Fault
def template FpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -137,7 +137,7 @@ Fault
def template DoFpOpExecute {{
Fault
%(class_name)s::doFpOp(ExecContext *xc, Trace::InstRecord *traceData) const
%(class_name)s::doFpOp(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

4
src/arch/sparc/isa/formats/branch.isa
View File

@@ -31,7 +31,7 @@
def template JumpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
Fault fault = NoFault;
@@ -53,7 +53,7 @@ def template JumpExecute {{
def template BranchExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
Fault fault = NoFault;

2
src/arch/sparc/isa/formats/integerop.isa
View File

@@ -40,7 +40,7 @@ def template SetHiDecode {{
def template IntOpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;

6
src/arch/sparc/isa/formats/mem/basicmem.isa
View File

@@ -45,11 +45,11 @@ def template MemDeclare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};

6
src/arch/sparc/isa/formats/mem/blockmem.isa
View File

@@ -61,10 +61,10 @@ def template BlockMemMicroDeclare {{
public:
// Constructor
%(class_name)s_%(micro_pc)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};

6
src/arch/sparc/isa/formats/mem/swap.isa
View File

@@ -27,7 +27,7 @@
// This template provides the execute functions for a swap
def template SwapExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
// This is to support the conditional store in cas instructions.
@@ -65,7 +65,7 @@ def template SwapExecute {{
def template SwapInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -93,7 +93,7 @@ def template SwapInitiateAcc {{
def template SwapCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

12
src/arch/sparc/isa/formats/mem/util.isa
View File

@@ -32,7 +32,7 @@
// This template provides the execute functions for a load
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -59,7 +59,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -78,7 +78,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -95,7 +95,7 @@ def template LoadCompleteAcc {{
// This template provides the execute functions for a store
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
// This is to support the conditional store in cas instructions.
@@ -126,7 +126,7 @@ def template StoreExecute {{
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
Fault fault = NoFault;
bool storeCond = true;
@@ -151,7 +151,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
return NoFault;
}

2
src/arch/sparc/isa/formats/priv.isa
View File

@@ -40,7 +40,7 @@ def template ControlRegConstructor {{
def template PrivExecute {{
Fault
%(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const
%(class_name)s::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;

4
src/arch/sparc/isa/formats/trap.isa
View File

@@ -32,7 +32,7 @@
def template TrapExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -45,7 +45,7 @@ def template TrapExecute {{
def template FpUnimplExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

6
src/arch/sparc/nativetrace.cc
View File

@@ -37,7 +37,7 @@
namespace gem5
{
namespace Trace {
namespace trace {
static const char *intRegNames[SparcISA::int_reg::NumArchRegs] = {
// Global registers
@@ -51,7 +51,7 @@ static const char *intRegNames[SparcISA::int_reg::NumArchRegs] = {
};
void
Trace::SparcNativeTrace::check(NativeTraceRecord *record)
SparcNativeTrace::check(NativeTraceRecord *record)
{
ThreadContext *tc = record->getThread();
@@ -89,5 +89,5 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record)
checkReg("ccr", regVal, realRegVal);
}
} // namespace Trace
} // namespace trace
} // namespace gem5

4
src/arch/sparc/nativetrace.hh
View File

@@ -37,7 +37,7 @@ namespace gem5
class ThreadContext;
namespace Trace {
namespace trace {
class SparcNativeTrace : public NativeTrace
{
@@ -48,7 +48,7 @@ class SparcNativeTrace : public NativeTrace
void check(NativeTraceRecord *record);
};
} // namespace Trace
} // namespace trace
} // namespace gem5
#endif // __CPU_NATIVETRACE_HH__

2
src/arch/x86/X86NativeTrace.py
View File

@@ -32,5 +32,5 @@ from m5.objects.CPUTracers import NativeTrace
class X86NativeTrace(NativeTrace):
type = "X86NativeTrace"
cxx_class = "gem5::Trace::X86NativeTrace"
cxx_class = "gem5::trace::X86NativeTrace"
cxx_header = "arch/x86/nativetrace.hh"

2
src/arch/x86/insts/decode_fault.hh
View File

@@ -58,7 +58,7 @@ class DecodeFaultInst : public X86StaticInst
{}
Fault
execute(ExecContext *tc, Trace::InstRecord *traceData) const override
execute(ExecContext *tc, trace::InstRecord *traceData) const override
{
return fault;
}

2
src/arch/x86/insts/microdebug.hh
View File

@@ -49,7 +49,7 @@ class MicroDebug : public X86ISA::X86MicroopBase
{}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return fault;
}

2
src/arch/x86/insts/microspecop.hh
View File

@@ -49,7 +49,7 @@ class MicroHalt : public InstOperands<X86MicroopBase>
{}
Fault
execute(ExecContext *xc, Trace::InstRecord *) const override
execute(ExecContext *xc, trace::InstRecord *) const override
{
xc->tcBase()->suspend();
return NoFault;

4
src/arch/x86/isa/formats/basic.isa
View File

@@ -49,7 +49,7 @@ def template BasicDeclare {{
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -66,7 +66,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;

2
src/arch/x86/isa/formats/cpuid.isa
View File

@@ -66,7 +66,7 @@ output decoder {{
def template CPUIDExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
// If the CPUID instruction used a valid function number, this will
// be set to true. Otherwise, the instruction does nothing.

10
src/arch/x86/isa/formats/monitor_mwait.isa
View File

@@ -51,16 +51,16 @@ def template MwaitDeclare {{
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
trace::InstRecord *) const override;
};
}};
def template MwaitInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
Trace::InstRecord * traceData) const
trace::InstRecord * traceData) const
{
unsigned s = 0x8; //size
unsigned f = 0; //flags
@@ -71,7 +71,7 @@ def template MwaitInitiateAcc {{
def template MwaitCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
MicroHalt hltObj(machInst, mnemonic, 0x0);
if(xc->mwait(pkt)) {

2
src/arch/x86/isa/formats/nop.isa
View File

@@ -71,7 +71,7 @@ output decoder {{
def template NopExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
return NoFault;
}

2
src/arch/x86/isa/formats/syscall.isa
View File

@@ -71,7 +71,7 @@ output decoder {{
def template SyscallExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;

8
src/arch/x86/isa/formats/unimp.isa
View File

@@ -60,7 +60,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -92,7 +92,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -119,7 +119,7 @@ output decoder {{
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' %s",
mnemonic, machInst);
@@ -128,7 +128,7 @@ output exec {{
Fault
WarnUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);

4
src/arch/x86/isa/formats/unknown.isa
View File

@@ -55,7 +55,7 @@ output header {{
{
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -74,7 +74,7 @@ output decoder {{
output exec {{
Fault
Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<InvalidOpcode>();
}

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