misc: Fix 'unused variable' clang errors with gem5.fast

Change-Id: I2bb8ac10e8db69fa82abe41577cd8e5db575e93d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70297
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

src/arch/arm/self_debug.cc

@@ -127,9 +127,7 @@ SelfDebug::testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
         return NoFault;
 
     ExceptionLevel el = (ExceptionLevel) currEL(tc);
-    int idxtmp = -1;
     for (auto &p: arWatchPoints){
-        idxtmp ++;
         if (p.enable) {
             if (p.test(tc, vaddr, el, write, atomic, size)) {
                 return triggerWatchpointException(tc, vaddr, write, cm);

src/arch/sparc/faults.cc

@@ -302,7 +302,6 @@ enterREDState(ThreadContext *tc)
 void
 doREDFault(ThreadContext *tc, TrapType tt)
 {
-    RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
     RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
@@ -313,8 +312,6 @@ doREDFault(ThreadContext *tc, TrapType tt)
     RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
     auto &pc = tc->pcState().as<PCState>();
 
-    TL++;
-
     Addr pcMask = pstate.am ? mask(32) : mask(64);
 
     // set TSTATE.gl to gl

src/cpu/activity.cc

@@ -151,6 +151,7 @@ ActivityRecorder::dump()
 void
 ActivityRecorder::validate()
 {
+#ifdef DEBUG
     int count = 0;
     for (int i = 0; i <= longestLatency; ++i) {
         if (activityBuffer[-i]) {
@@ -165,6 +166,7 @@ ActivityRecorder::validate()
     }
 
     assert(count == activityCount);
+#endif
 }
 
 } // namespace gem5

src/cpu/minor/execute.cc

@@ -568,10 +568,6 @@ Execute::issue(ThreadID thread_id)
     /* Number of memory ops issues this cycle to check for memoryIssueLimit */
     unsigned num_mem_insts_issued = 0;
 
-    /* Number of instructions discarded this cycle in order to enforce a
-     *  discardLimit. @todo, add that parameter? */
-    unsigned num_insts_discarded = 0;
-
     do {
         MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
         Fault fault = inst->fault;
@@ -800,9 +796,7 @@ Execute::issue(ThreadID thread_id)
             if (issued_mem_ref)
                 num_mem_insts_issued++;
 
-            if (discarded) {
-                num_insts_discarded++;
-            } else if (!inst->isBubble()) {
+            if (!discarded && !inst->isBubble()) {
                 num_insts_issued++;
 
                 if (num_insts_issued == issueLimit)

src/cpu/simple/atomic.cc

@@ -462,7 +462,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
     Addr frag_addr = addr;
     int frag_size = 0;
     int size_left = size;
-    int curr_frag_id = 0;
+    [[maybe_unused]] int curr_frag_id = 0;
     bool predicate;
     Fault fault = NoFault;
 

src/dev/storage/ide_disk.cc

@@ -1072,7 +1072,7 @@ IdeDisk::serialize(CheckpointOut &cp) const
     Tick reschedule = 0;
     Events_t event = None;
 
-    int eventCount = 0;
+    [[maybe_unused]] int eventCount = 0;
 
     if (dmaTransferEvent.scheduled()) {
         reschedule = dmaTransferEvent.when();

src/mem/ruby/system/Sequencer.cc

@@ -464,8 +464,6 @@ Sequencer::writeCallback(Addr address, DataBlock& data,
     // ruby request was outstanding. Since only 1 ruby request was made,
     // profile the ruby latency once.
     bool ruby_request = true;
-    int aliased_stores = 0;
-    int aliased_loads = 0;
     while (!seq_req_list.empty()) {
         SequencerRequest &seq_req = seq_req_list.front();
 
@@ -520,9 +518,8 @@ Sequencer::writeCallback(Addr address, DataBlock& data,
                 recordMissLatency(&seq_req, success, mach, externalHit,
                                   initialRequestTime, forwardRequestTime,
                                   firstResponseTime);
-            } else {
-                aliased_stores++;
             }
+
             markRemoved();
             hitCallback(&seq_req, data, success, mach, externalHit,
                         initialRequestTime, forwardRequestTime,
@@ -532,7 +529,6 @@ Sequencer::writeCallback(Addr address, DataBlock& data,
             // handle read request
             assert(!ruby_request);
             markRemoved();
-            aliased_loads++;
             hitCallback(&seq_req, data, true, mach, externalHit,
                         initialRequestTime, forwardRequestTime,
                         firstResponseTime, !ruby_request);
@@ -565,15 +561,12 @@ Sequencer::readCallback(Addr address, DataBlock& data,
     // ruby request was outstanding. Since only 1 ruby request was made,
     // profile the ruby latency once.
     bool ruby_request = true;
-    int aliased_loads = 0;
     while (!seq_req_list.empty()) {
         SequencerRequest &seq_req = seq_req_list.front();
         if (ruby_request) {
             assert((seq_req.m_type == RubyRequestType_LD) ||
                    (seq_req.m_type == RubyRequestType_Load_Linked) ||
                    (seq_req.m_type == RubyRequestType_IFETCH));
-        } else {
-            aliased_loads++;
         }
         if ((seq_req.m_type != RubyRequestType_LD) &&
             (seq_req.m_type != RubyRequestType_Load_Linked) &&