misc: Replace TARGET_ISA with USE_${ISA} variables.

The TARGET_ISA variable would let you select one ISA from a list of
possible ISAs. That has now been replaced with USE_ARM_ISA, USE_X86_ISA,
etc, variables which are boolean on or off. That will allow any number
of ISAs to be enabled or disabled individually. Enabling something other
than exactly one of these will probably prevent you from getting a
working gem5 binary, but those problems are being addressed in other,
parallel change series.

I decided to use the USE_ prefix since it was consistent with most other
on/off variables we have in gem5. One noteable exception is the
BUILD_GPU setting which, you could convincingly argue, is a better
prefix than USE_. Another option would be to use CONFIG_, in
anticipation of using a kconfig style config mechanism in gem5.

It seemed premature to start using a CONFIG_ prefix here, and if we
decide to switch to some other prefix like BUILD_, it should be a
purposeful choice and not something somebody just starts using.

Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

build_opts/ARM

@@ -1,2 +1,2 @@
-TARGET_ISA = 'arm'
+USE_ARM_ISA = True
 PROTOCOL = 'CHI'

build_opts/ARM_MESI_Three_Level

@@ -1,5 +1,5 @@
 # Copyright (c) 2019 ARM Limited
 # All rights reserved.
 
-TARGET_ISA = 'arm'
+USE_ARM_ISA = True
 PROTOCOL = 'MESI_Three_Level'

build_opts/ARM_MESI_Three_Level_HTM

@@ -1,5 +1,5 @@
 # Copyright (c) 2019 ARM Limited
 # All rights reserved.
 
-TARGET_ISA = 'arm'
+USE_ARM_ISA = True
 PROTOCOL = 'MESI_Three_Level_HTM'

build_opts/ARM_MOESI_hammer

@@ -1,5 +1,5 @@
 # Copyright (c) 2019 ARM Limited
 # All rights reserved.
 
-TARGET_ISA = 'arm'
+USE_ARM_ISA = True
 PROTOCOL = 'MOESI_hammer'

build_opts/GCN3_X86

@@ -1,4 +1,4 @@
 PROTOCOL = 'GPU_VIPER'
-TARGET_ISA = 'x86'
+USE_X86_ISA = True
 TARGET_GPU_ISA = 'gcn3'
 BUILD_GPU = True

build_opts/Garnet_standalone

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL = 'Garnet_standalone'

build_opts/MIPS

@@ -1,2 +1,2 @@
-TARGET_ISA = 'mips'
+USE_MIPS_ISA = True
 PROTOCOL = 'MI_example'

build_opts/NULL

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL='MI_example'

build_opts/NULL_MESI_Two_Level

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL = 'MESI_Two_Level'

build_opts/NULL_MOESI_CMP_directory

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL='MOESI_CMP_directory'

build_opts/NULL_MOESI_CMP_token

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL='MOESI_CMP_token'

build_opts/NULL_MOESI_hammer

@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL_ISA = True
 PROTOCOL='MOESI_hammer'

build_opts/POWER

@@ -1,2 +1,2 @@
-TARGET_ISA = 'power'
+USE_POWER_ISA = True
 PROTOCOL = 'MI_example'

build_opts/RISCV

@@ -1,2 +1,2 @@
-TARGET_ISA = 'riscv'
+USE_RISCV_ISA = True
 PROTOCOL = 'MI_example'

build_opts/SPARC

@@ -1,2 +1,2 @@
-TARGET_ISA = 'sparc'
+USE_SPARC_ISA = True
 PROTOCOL = 'MI_example'

build_opts/VEGA_X86

@@ -1,4 +1,4 @@
 PROTOCOL = 'GPU_VIPER'
-TARGET_ISA = 'x86'
+USE_X86_ISA = True
 TARGET_GPU_ISA = 'vega'
 BUILD_GPU = True

build_opts/X86

@@ -1,3 +1,3 @@
-TARGET_ISA = 'x86'
+USE_X86_ISA = True
 PROTOCOL = 'MESI_Two_Level'
 NUMBER_BITS_PER_SET = '128'

build_opts/X86_MESI_Two_Level

@@ -1,3 +1,3 @@
-TARGET_ISA = 'x86'
+USE_X86_ISA = True
 PROTOCOL = 'MESI_Two_Level'
 NUMBER_BITS_PER_SET = '128'

build_opts/X86_MI_example

@@ -1,2 +1,2 @@
-TARGET_ISA = 'x86'
+USE_X86_ISA = True
 PROTOCOL = 'MI_example'

build_opts/X86_MOESI_AMD_Base

@@ -1,2 +1,2 @@
 PROTOCOL = 'MOESI_AMD_Base'
-TARGET_ISA = 'x86'
+USE_X86_ISA = True

configs/common/CacheConfig.py

@@ -42,6 +42,9 @@
 
 import m5
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
+
 from common.Caches import *
 from common import ObjectList
 
@@ -114,7 +117,7 @@ def config_cache(options, system):
             None,
         )
 
-        if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
+        if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
             walk_cache_class = PageTableWalkerCache
 
     # Set the cache line size of the system
@@ -189,7 +192,7 @@ def config_cache(options, system):
             # on these names.  For simplicity, we would advise configuring
             # it to use this naming scheme; if this isn't possible, change
             # the names below.
-            if buildEnv["TARGET_ISA"] in ["x86", "arm", "riscv"]:
+            if get_runtime_isa() in [ISA.X86, ISA.ARM, ISA.RISCV]:
                 system.cpu[i].addPrivateSplitL1Caches(
                     ExternalCache("cpu%d.icache" % i),
                     ExternalCache("cpu%d.dcache" % i),

configs/common/Caches.py

@@ -39,6 +39,8 @@
 
 from m5.defines import buildEnv
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # Base implementations of L1, L2, IO and TLB-walker caches. There are
 # used in the regressions and also as base components in the
@@ -96,7 +98,7 @@ class PageTableWalkerCache(Cache):
     tgts_per_mshr = 12
 
     # the x86 table walker actually writes to the table-walker cache
-    if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
+    if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
         is_read_only = False
     else:
         is_read_only = True

configs/common/FSConfig.py

@@ -39,26 +39,35 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
+import m5.defines
 from m5.objects import *
 from m5.util import *
 from common.Benchmarks import *
 from common import ObjectList
 
 # Populate to reflect supported os types per target ISA
-os_types = {
-    "mips": ["linux"],
-    "riscv": ["linux"],  # TODO that's a lie
-    "sparc": ["linux"],
-    "x86": ["linux"],
-    "arm": [
-        "linux",
-        "android-gingerbread",
-        "android-ics",
-        "android-jellybean",
-        "android-kitkat",
-        "android-nougat",
-    ],
-}
+os_types = set()
+if m5.defines.buildEnv["USE_ARM_ISA"]:
+    os_types.update(
+        [
+            "linux",
+            "android-gingerbread",
+            "android-ics",
+            "android-jellybean",
+            "android-kitkat",
+            "android-nougat",
+        ]
+    )
+if m5.defines.buildEnv["USE_MIPS_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_POWER_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_RISCV_ISA"]:
+    os_types.add("linux")  # TODO that's a lie
+if m5.defines.buildEnv["USE_SPARC_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_X86_ISA"]:
+    os_types.add("linux")
 
 
 class CowIdeDisk(IdeDisk):

configs/common/ObjectList.py

@@ -34,6 +34,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from gem5.runtime import get_supported_isas
 import m5.objects
 import m5.internal.params
 import inspect
@@ -139,13 +140,14 @@ class CPUList(ObjectList):
     def _add_objects(self):
         super(CPUList, self)._add_objects()
 
-        from m5.defines import buildEnv
         from importlib import import_module
 
-        for package in ["generic", buildEnv["TARGET_ISA"]]:
+        for isa in {
+            "generic",
+        } | {isa.name.lower() for isa in get_supported_isas()}:
             try:
                 package = import_module(
-                    ".cores." + package, package=__name__.rpartition(".")[0]
+                    ".cores." + isa, package=__name__.rpartition(".")[0]
                 )
             except ImportError:
                 # No timing models for this ISA

configs/common/Options.py

@@ -772,7 +772,7 @@ def addFSOptions(parser):
     parser.add_argument(
         "--os-type",
         action="store",
-        choices=os_types[str(buildEnv["TARGET_ISA"])],
+        choices=os_types,
         default="linux",
         help="Specifies type of OS to boot",
     )
@@ -784,7 +784,7 @@ def addFSOptions(parser):
         "files in the gem5 output directory",
     )
 
-    if buildEnv["TARGET_ISA"] == "arm":
+    if buildEnv["USE_ARM_ISA"]:
         parser.add_argument(
             "--bare-metal",
             action="store_true",

configs/example/apu_se.py

@@ -35,6 +35,8 @@ import inspect
 import m5
 from m5.objects import *
 from m5.util import addToPath
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
@@ -738,7 +740,7 @@ system.clk_domain = SrcClockDomain(
 
 if fast_forward:
     have_kvm_support = "BaseKvmCPU" in globals()
-    if have_kvm_support and buildEnv["TARGET_ISA"] == "x86":
+    if have_kvm_support and get_runtime_isa() == ISA.X86:
         system.vm = KvmVM()
         system.m5ops_base = 0xFFFF0000
         for i in range(len(host_cpu.workload)):
@@ -777,7 +779,7 @@ for i in range(args.num_cpus):
     system.cpu[i].dcache_port = ruby_port.in_ports
 
     ruby_port.mem_request_port = system.piobus.cpu_side_ports
-    if buildEnv["TARGET_ISA"] == "x86":
+    if get_runtime_isa() == ISA.X86:
         system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
         system.cpu[i].interrupts[
             0

configs/example/fs.py

@@ -47,6 +47,8 @@ from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import addToPath, fatal, warn
 from m5.util.fdthelper import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
@@ -80,19 +82,20 @@ def cmd_line_template():
 
 def build_test_system(np):
     cmdline = cmd_line_template()
-    if buildEnv["TARGET_ISA"] == "mips":
+    isa = get_runtime_isa()
+    if isa == ISA.MIPS:
         test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
-    elif buildEnv["TARGET_ISA"] == "sparc":
+    elif isa == ISA.SPARC:
         test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
-    elif buildEnv["TARGET_ISA"] == "riscv":
+    elif isa == ISA.RISCV:
         test_sys = makeBareMetalRiscvSystem(
             test_mem_mode, bm[0], cmdline=cmdline
         )
-    elif buildEnv["TARGET_ISA"] == "x86":
+    elif isa == ISA.X86:
         test_sys = makeLinuxX86System(
             test_mem_mode, np, bm[0], args.ruby, cmdline=cmdline
         )
-    elif buildEnv["TARGET_ISA"] == "arm":
+    elif isa == ISA.ARM:
         test_sys = makeArmSystem(
             test_mem_mode,
             args.machine_type,
@@ -109,7 +112,7 @@ def build_test_system(np):
         if args.enable_context_switch_stats_dump:
             test_sys.enable_context_switch_stats_dump = True
     else:
-        fatal("Incapable of building %s full system!", buildEnv["TARGET_ISA"])
+        fatal("Incapable of building %s full system!", isa.name)
 
     # Set the cache line size for the entire system
     test_sys.cache_line_size = args.cacheline_size
@@ -130,7 +133,7 @@ def build_test_system(np):
         clock=args.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain
     )
 
-    if buildEnv["TARGET_ISA"] == "riscv":
+    if buildEnv["USE_RISCV_ISA"]:
         test_sys.workload.bootloader = args.kernel
     elif args.kernel is not None:
         test_sys.workload.object_file = binary(args.kernel)
@@ -255,15 +258,15 @@ def build_drive_system(np):
     DriveMemClass = SimpleMemory
 
     cmdline = cmd_line_template()
-    if buildEnv["TARGET_ISA"] == "mips":
+    if buildEnv["USE_MIPS_ISA"]:
         drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
-    elif buildEnv["TARGET_ISA"] == "sparc":
+    elif buildEnv["USE_SPARC_ISA"]:
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
-    elif buildEnv["TARGET_ISA"] == "x86":
+    elif buildEnv["USE_X86_ISA"]:
         drive_sys = makeLinuxX86System(
             drive_mem_mode, np, bm[1], cmdline=cmdline
         )
-    elif buildEnv["TARGET_ISA"] == "arm":
+    elif buildEnv["USE_ARM_ISA"]:
         drive_sys = makeArmSystem(
             drive_mem_mode,
             args.machine_type,
@@ -407,11 +410,7 @@ if args.timesync:
 if args.frame_capture:
     VncServer.frame_capture = True
 
-if (
-    buildEnv["TARGET_ISA"] == "arm"
-    and not args.bare_metal
-    and not args.dtb_filename
-):
+if buildEnv["USE_ARM_ISA"] and not args.bare_metal and not args.dtb_filename:
     if args.machine_type not in [
         "VExpress_GEM5",
         "VExpress_GEM5_V1",

configs/example/hmc_hello.py

@@ -36,8 +36,10 @@ import argparse
 import m5
 from m5.objects import *
 from m5.util import *
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
+
 from common import MemConfig
 from common import HMC
 
@@ -67,9 +69,9 @@ system.cpu.createInterruptController()
 # functional-only port to allow the system to read and write memory.
 system.system_port = system.membus.cpu_side_ports
 # get ISA for the binary to run.
-isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
+isa = get_runtime_isa()
 # run 'hello' and use the compiled ISA to find the binary
-binary = "tests/test-progs/hello/bin/" + isa + "/linux/hello"
+binary = "tests/test-progs/hello/bin/" + isa.name.lower() + "/linux/hello"
 # create a process for a simple "Hello World" application
 process = Process()
 # cmd is a list which begins with the executable (like argv)

configs/example/se.py

@@ -49,6 +49,8 @@ from m5.defines import buildEnv
 from m5.objects import *
 from m5.params import NULL
 from m5.util import addToPath, fatal, warn
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
@@ -137,12 +139,14 @@ if args.bench:
 
     for app in apps:
         try:
-            if buildEnv["TARGET_ISA"] == "arm":
+            if get_runtime_isa() == ISA.ARM:
                 exec(
                     "workload = %s('arm_%s', 'linux', '%s')"
                     % (app, args.arm_iset, args.spec_input)
                 )
             else:
+                # TARGET_ISA has been removed, but this is missing a ], so it
+                # has incorrect syntax and wasn't being used anyway.
                 exec(
                     "workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')"
                     % (app, args.spec_input)
@@ -151,7 +155,7 @@ if args.bench:
         except:
             print(
                 "Unable to find workload for %s: %s"
-                % (buildEnv["TARGET_ISA"], app),
+                % (get_runtime_isa().name(), app),
                 file=sys.stderr,
             )
             sys.exit(1)
@@ -208,7 +212,7 @@ for cpu in system.cpu:
     cpu.clk_domain = system.cpu_clk_domain
 
 if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
-    if buildEnv["TARGET_ISA"] == "x86":
+    if buildEnv["USE_X86_ISA"]:
         system.kvm_vm = KvmVM()
         system.m5ops_base = 0xFFFF0000
         for process in multiprocesses:

configs/learning_gem5/part1/simple.py

@@ -40,6 +40,8 @@ import m5
 
 # import all of the SimObjects
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # create the system we are going to simulate
 system = System()
@@ -68,7 +70,7 @@ system.cpu.createInterruptController()
 
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv["TARGET_ISA"] == "x86":
+if get_runtime_isa() == ISA.X86:
     system.cpu.interrupts[0].pio = system.membus.mem_side_ports
     system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
     system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
@@ -83,13 +85,17 @@ system.mem_ctrl.port = system.membus.mem_side_ports
 system.system_port = system.membus.cpu_side_ports
 
 # get ISA for the binary to run.
-isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
+isa = get_runtime_isa()
 
 # Default to running 'hello', use the compiled ISA to find the binary
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 binary = os.path.join(
-    thispath, "../../../", "tests/test-progs/hello/bin/", isa, "linux/hello"
+    thispath,
+    "../../../",
+    "tests/test-progs/hello/bin/",
+    isa.name.lower(),
+    "linux/hello",
 )
 
 system.workload = SEWorkload.init_compatible(binary)

configs/learning_gem5/part1/two_level.py

@@ -43,6 +43,8 @@ import m5
 
 # import all of the SimObjects
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # Add the common scripts to our path
 m5.util.addToPath("../../")
@@ -54,13 +56,17 @@ from caches import *
 from common import SimpleOpts
 
 # get ISA for the default binary to run. This is mostly for simple testing
-isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
+isa = get_runtime_isa()
 
 # Default to running 'hello', use the compiled ISA to find the binary
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
 default_binary = os.path.join(
-    thispath, "../../../", "tests/test-progs/hello/bin/", isa, "linux/hello"
+    thispath,
+    "../../../",
+    "tests/test-progs/hello/bin/",
+    isa.name.lower(),
+    "linux/hello",
 )
 
 # Binary to execute
@@ -114,7 +120,7 @@ system.cpu.createInterruptController()
 
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv["TARGET_ISA"] == "x86":
+if isa == ISA.X86:
     system.cpu.interrupts[0].pio = system.membus.mem_side_ports
     system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
     system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports

configs/learning_gem5/part3/msi_caches.py

@@ -39,6 +39,8 @@ import math
 
 from m5.defines import buildEnv
 from m5.util import fatal, panic
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 from m5.objects import *
 
@@ -147,7 +149,7 @@ class L1Cache(L1Cache_Controller):
         2. The x86 mwait instruction is built on top of coherence
         3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
+        if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM):
             return True
         return False
 

configs/learning_gem5/part3/ruby_caches_MI_example.py

@@ -41,6 +41,8 @@ import math
 
 from m5.defines import buildEnv
 from m5.util import fatal, panic
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 from m5.objects import *
 
@@ -145,7 +147,7 @@ class L1Cache(L1Cache_Controller):
         2. The x86 mwait instruction is built on top of coherence
         3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
+        if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM):
             return True
         return False
 

configs/learning_gem5/part3/simple_ruby.py

@@ -42,6 +42,7 @@ import m5
 
 # import all of the SimObjects
 from m5.objects import *
+from gem5.runtime import get_runtime_isa
 
 # Needed for running C++ threads
 m5.util.addToPath("../../")
@@ -80,7 +81,7 @@ system.caches = MyCacheSystem()
 system.caches.setup(system, system.cpu, [system.mem_ctrl])
 
 # get ISA for the binary to run.
-isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
+isa = get_runtime_isa()
 
 # Run application and use the compiled ISA to find the binary
 # grab the specific path to the binary
@@ -89,7 +90,7 @@ binary = os.path.join(
     thispath,
     "../../../",
     "tests/test-progs/threads/bin/",
-    isa,
+    isa.name.lower(),
     "linux/threads",
 )
 

configs/ruby/Ruby.py

@@ -42,6 +42,8 @@ import m5
 from m5.objects import *
 from m5.defines import buildEnv
 from m5.util import addToPath, fatal
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
@@ -324,9 +326,9 @@ def send_evicts(options):
     # 1. The O3 model must keep the LSQ coherent with the caches
     # 2. The x86 mwait instruction is built on top of coherence invalidations
     # 3. The local exclusive monitor in ARM systems
-    if options.cpu_type == "DerivO3CPU" or buildEnv["TARGET_ISA"] in (
-        "x86",
-        "arm",
+    if options.cpu_type == "DerivO3CPU" or get_runtime_isa() in (
+        ISA.X86,
+        ISA.ARM,
     ):
         return True
     return False

src/arch/SConscript

@@ -56,7 +56,27 @@ Import('*')
 #
 #################################################################
 
-env.TagImplies(env.subst('${CONF["TARGET_ISA"]} isa'), 'gem5 lib')
+if env['CONF']['USE_ARM_ISA']:
+    env.TagImplies('arm isa', 'gem5 lib')
+    isa = 'arm'
+elif env['CONF']['USE_MIPS_ISA']:
+    env.TagImplies('mips isa', 'gem5 lib')
+    isa = 'mips'
+elif env['CONF']['USE_POWER_ISA']:
+    env.TagImplies('power isa', 'gem5 lib')
+    isa = 'power'
+elif env['CONF']['USE_RISCV_ISA']:
+    env.TagImplies('riscv isa', 'gem5 lib')
+    isa = 'riscv'
+elif env['CONF']['USE_SPARC_ISA']:
+    env.TagImplies('sparc isa', 'gem5 lib')
+    isa = 'sparc'
+elif env['CONF']['USE_X86_ISA']:
+    env.TagImplies('x86 isa', 'gem5 lib')
+    isa = 'x86'
+elif env['CONF']['USE_NULL_ISA']:
+    env.TagImplies('null isa', 'gem5 lib')
+    isa = 'null'
 
 amdgpu_isa = ['gcn3', 'vega']
 

src/arch/SConsopts

@@ -27,8 +27,6 @@ Import('*')
 
 def add_isa_lists():
     sticky_vars.AddVariables(
-        EnumVariable('TARGET_ISA', 'Target ISA', 'null',
-            sorted(set(main.Split('${ALL_ISAS}')))),
         EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'gcn3',
             sorted(set(main.Split('${ALL_GPU_ISAS}')))),
         )

src/arch/arm/SConscript

@@ -45,7 +45,7 @@ Import('*')
 #
 # Note: This will need reconfigured for multi-isa. E.g., if this is
 # incorporated: https://gem5-review.googlesource.com/c/public/gem5/+/52491
-if env['TARGET_ISA'] == 'arm':
+if env['USE_ARM_ISA']:
     GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc',
             '../../cpu/reg_class.cc', '../../sim/bufval.cc')
 Source('decoder.cc', tags='arm isa')

src/arch/arm/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007-2008 The Florida State University
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,4 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['arm'])
+sticky_vars.Add(BoolVariable('USE_ARM_ISA', 'Enable ARM ISA support', False))

src/arch/mips/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,4 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['mips'])
+sticky_vars.Add(BoolVariable('USE_MIPS_ISA', 'Enable MIPS ISA support', False))

src/arch/null/SConsopts

@@ -1,16 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2013 ARM Limited
-# All rights reserved
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -36,5 +24,4 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['null'])
+sticky_vars.Add(BoolVariable('USE_NULL_ISA', 'Enable NULL ISA support', False))

src/arch/power/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2009 The University of Edinburgh
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['power'])
+sticky_vars.Add(BoolVariable('USE_POWER_ISA', 'Enable POWER ISA support',
+    False))

src/arch/riscv/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['riscv'])
+sticky_vars.Add(BoolVariable('USE_RISCV_ISA', 'Enable RISC-V ISA support',
+    False))

src/arch/sparc/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['sparc'])
+sticky_vars.Add(BoolVariable('USE_SPARC_ISA', 'Enable SPARC ISA support',
+    False))

src/arch/x86/SConsopts

@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007 The Hewlett-Packard Development Company
-# All rights reserved.
+# Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
@@ -27,5 +24,4 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 Import('*')
-
-main.Append(ALL_ISAS=['x86'])
+sticky_vars.Add(BoolVariable('USE_X86_ISA', 'Enable X86 ISA support', False))

src/arch/x86/kvm/SConscript

@@ -37,8 +37,7 @@
 
 Import('*')
 
-if not env['CONF']['USE_KVM'] or \
-        env['CONF']['TARGET_ISA'] != env['CONF']['KVM_ISA']:
+if not env['CONF']['USE_KVM'] or env['CONF']['KVM_ISA'] != 'x86':
     Return()
 
 SimObject('X86KvmCPU.py', sim_objects=['X86KvmCPU'], tags='x86 isa')

src/cpu/kvm/SConscript

@@ -37,8 +37,11 @@
 
 Import('*')
 
-if not env['CONF']['USE_KVM'] or \
-        env['CONF']['TARGET_ISA'] != env['CONF']['KVM_ISA']:
+if not env['CONF']['USE_KVM']:
+    Return()
+
+kvm_isa = env['CONF']['KVM_ISA']
+if not env['CONF'][f'USE_{kvm_isa.upper()}_ISA']:
     Return()
 
 SimObject('KvmVM.py', sim_objects=['KvmVM'])

src/cpu/minor/SConscript

@@ -40,7 +40,7 @@
 
 Import('*')
 
-if env['CONF']['TARGET_ISA'] != 'null':
+if not env['CONF']['USE_NULL_ISA']:
     SimObject('BaseMinorCPU.py', sim_objects=[
         'MinorOpClass', 'MinorOpClassSet', 'MinorFUTiming', 'MinorFU',
         'MinorFUPool', 'BaseMinorCPU'],

src/cpu/o3/FuncUnitConfig.py

@@ -58,7 +58,7 @@ class IntMultDiv(FUDesc):
     # issues division microops.  The latency of these microops should really be
     # one (or a small number) cycle each since each of these computes one bit
     # of the quotient.
-    if buildEnv["TARGET_ISA"] in ("x86"):
+    if buildEnv["USE_X86_ISA"]:
         opList[1].opLat = 1
 
     count = 2

src/cpu/o3/SConscript

@@ -30,7 +30,7 @@ import sys
 
 Import('*')
 
-if env['CONF']['TARGET_ISA'] != 'null':
+if not env['CONF']['USE_NULL_ISA']:
     SimObject('FUPool.py', sim_objects=['FUPool'])
     SimObject('FuncUnitConfig.py', sim_objects=[])
     SimObject('BaseO3CPU.py', sim_objects=['BaseO3CPU'], enums=[

src/cpu/o3/probe/SConscript

@@ -37,7 +37,7 @@
 
 Import('*')
 
-if env['CONF']['TARGET_ISA'] != 'null':
+if not env['CONF']['USE_NULL_ISA']:
     SimObject('SimpleTrace.py', sim_objects=['SimpleTrace'])
     Source('simple_trace.cc')
     DebugFlag('SimpleTrace')

src/cpu/simple/SConscript

@@ -28,7 +28,7 @@
 
 Import('*')
 
-if env['CONF']['TARGET_ISA'] != 'null':
+if not env['CONF']['USE_NULL_ISA']:
     SimObject('BaseAtomicSimpleCPU.py', sim_objects=['BaseAtomicSimpleCPU'])
     Source('atomic.cc')
 

src/cpu/simple/probes/SConscript

@@ -28,6 +28,6 @@
 
 Import('*')
 
-if env['CONF']['TARGET_ISA'] != 'null':
+if not env['CONF']['USE_NULL_ISA']:
     SimObject('SimPoint.py', sim_objects=['SimPoint'])
     Source('simpoint.cc')

tests/configs/o3-timing-mt.py

@@ -41,11 +41,13 @@ from m5.defines import buildEnv
 from base_config import *
 from arm_generic import *
 from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # If we are running ARM regressions, use a more sensible CPU
 # configuration. This makes the results more meaningful, and also
 # increases the coverage of the regressions.
-if buildEnv["TARGET_ISA"] == "arm":
+if get_runtime_isa() == ISA.ARM:
     root = ArmSESystemUniprocessor(
         mem_mode="timing",
         mem_class=DDR3_1600_8x8,

tests/configs/o3-timing.py

@@ -41,11 +41,13 @@ from m5.defines import buildEnv
 from base_config import *
 from arm_generic import *
 from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # If we are running ARM regressions, use a more sensible CPU
 # configuration. This makes the results more meaningful, and also
 # increases the coverage of the regressions.
-if buildEnv["TARGET_ISA"] == "arm":
+if get_runtime_isa() == ISA.ARM:
     root = ArmSESystemUniprocessor(
         mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=O3_ARM_v7a_3
     ).create_root()

tests/gem5/cpu_tests/run.py

@@ -29,6 +29,8 @@ import os
 import argparse
 
 import m5
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 from m5.objects import *
 
 
@@ -97,7 +99,7 @@ class MySimpleMemory(SimpleMemory):
     latency = "1ns"
 
 
-if buildEnv["TARGET_ISA"] == "x86":
+if get_runtime_isa() == ISA.X86:
     valid_cpu = {
         "AtomicSimpleCPU": AtomicSimpleCPU,
         "TimingSimpleCPU": TimingSimpleCPU,
@@ -155,7 +157,7 @@ else:
     system.l2cache.connectMemSideBus(system.membus)
 
 system.cpu.createInterruptController()
-if m5.defines.buildEnv["TARGET_ISA"] == "x86":
+if get_runtime_isa() == ISA.X86:
     system.cpu.interrupts[0].pio = system.membus.mem_side_ports
     system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports
     system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports