derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: XPACD, XPACI, XPACLRI do not trap

Browse Source 
The HCR_EL2.API and SCR_EL3.API bits do not control the trapping of
those stripping instructions.

Change-Id: I84349937f8c50d63b5b52146743b035d1058fd8d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34055
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2020-08-25 12:02:56 +01:00
parent 5bbc326423
commit 0ad684a6f2
3 changed files with 11 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/isa/insts/pauth.isa
View File

@@ -90,7 +90,7 @@ let {{
code = pacEnabledCode(hint) + """
uint64_t res;
fault = stripPAC(xc->tcBase(), XDest, data, &res);
stripPAC(xc->tcBase(), XDest, data, &res);
XDest = res;
"""
regoptype = 'RegOp'

54
src/arch/arm/pauth_helpers.cc
View File

@@ -1,5 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2020 ARM Limited
// Copyright (c) 2020 Metempsy Technology Consulting
// All rights reserved
//
@@ -859,13 +860,9 @@ ArmISA::addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out){
Fault
ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){
bool trapEL2 = false;
bool trapEL3 = false;
uint64_t ptr;
void
ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out)
{
ExceptionLevel el = currEL(tc);
bool tbi = calculateTBI(tc, el, A, data);
@@ -873,52 +870,15 @@ ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){
int bottom_PAC_bit = calculateBottomPACBit(tc, el, selbit);
int top_bit = tbi ? 55 : 63;
uint32_t nbits = (top_bit+1) - bottom_PAC_bit;
uint32_t nbits = (top_bit + 1) - bottom_PAC_bit;
uint64_t pacbits = ((uint64_t)0x1 << nbits) -1; // 2^n -1;
uint64_t mask = pacbits << bottom_PAC_bit; // creates mask
if (selbit) {
ptr = A | mask;
*out = A | mask;
} else {
ptr = A & ~mask;
*out = A & ~mask;
}
SCR scr3 = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool have_el3 = ArmSystem::haveEL(tc, EL3);
switch (el)
{
case EL0:
trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
(hcr.tge == 0 || hcr.e2h == 0));
trapEL3 = have_el3 && scr3.api == 0;
break;
case EL1:
trapEL2 = EL2Enabled(tc) && hcr.api == 0;
trapEL3 = have_el3 && scr3.api == 0;
break;
case EL2:
trapEL2 = false;
trapEL3 = have_el3 && scr3.api == 0;
break;
case EL3:
trapEL2 = false;
trapEL3 = false;
break;
default:
// Unnaccessible
break;
}
if (trapEL2)
return trapPACUse(tc, EL2);
else if (trapEL3)
return trapPACUse(tc, EL3);
else
*out = ptr;
return NoFault;
}
} // namespace gem5

8
src/arch/arm/pauth_helpers.hh
View File

@@ -1,5 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2020 ARM Limited
// Copyright (c) 2020 Metempsy Technology Consulting
// All rights reserved
//
@@ -113,15 +114,12 @@ namespace ArmISA
Fault
addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out);
// Strip()
// =======
// Strip() returns a 64-bit value containing A, but replacing the
// stripPAC returns a 64-bit value containing A, but replacing the
// pointer authentication code field bits with the extension of the
// address bits. This can apply to either instructions or data, where,
// as the use of tagged pointers is distinct, it might be
// handled differently.
Fault
void
stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out);
} // namespace ArmISA