From 0ad684a6f27616ed1cd164ab102217657f2ed3b3 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 25 Aug 2020 12:02:56 +0100 Subject: [PATCH] arch-arm: XPACD, XPACI, XPACLRI do not trap The HCR_EL2.API and SCR_EL3.API bits do not control the trapping of those stripping instructions. Change-Id: I84349937f8c50d63b5b52146743b035d1058fd8d Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34055 Tested-by: kokoro Maintainer: Andreas Sandberg Reviewed-by: Kaustav Goswami Reviewed-by: Andreas Sandberg --- src/arch/arm/isa/insts/pauth.isa | 2 +- src/arch/arm/pauth_helpers.cc | 54 +++++--------------------------- src/arch/arm/pauth_helpers.hh | 8 ++--- 3 files changed, 11 insertions(+), 53 deletions(-) diff --git a/src/arch/arm/isa/insts/pauth.isa b/src/arch/arm/isa/insts/pauth.isa index ea16ab999d..830991deae 100644 --- a/src/arch/arm/isa/insts/pauth.isa +++ b/src/arch/arm/isa/insts/pauth.isa @@ -90,7 +90,7 @@ let {{ code = pacEnabledCode(hint) + """ uint64_t res; - fault = stripPAC(xc->tcBase(), XDest, data, &res); + stripPAC(xc->tcBase(), XDest, data, &res); XDest = res; """ regoptype = 'RegOp' diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc index c204a07808..7b3270c20d 100644 --- a/src/arch/arm/pauth_helpers.cc +++ b/src/arch/arm/pauth_helpers.cc @@ -1,5 +1,6 @@ // -*- mode:c++ -*- +// Copyright (c) 2020 ARM Limited // Copyright (c) 2020 Metempsy Technology Consulting // All rights reserved // @@ -859,13 +860,9 @@ ArmISA::addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out){ -Fault -ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){ - bool trapEL2 = false; - bool trapEL3 = false; - - uint64_t ptr; - +void +ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out) +{ ExceptionLevel el = currEL(tc); bool tbi = calculateTBI(tc, el, A, data); @@ -873,52 +870,15 @@ ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){ int bottom_PAC_bit = calculateBottomPACBit(tc, el, selbit); int top_bit = tbi ? 55 : 63; - uint32_t nbits = (top_bit+1) - bottom_PAC_bit; + uint32_t nbits = (top_bit + 1) - bottom_PAC_bit; uint64_t pacbits = ((uint64_t)0x1 << nbits) -1; // 2^n -1; uint64_t mask = pacbits << bottom_PAC_bit; // creates mask - if (selbit) { - ptr = A | mask; + *out = A | mask; } else { - ptr = A & ~mask; + *out = A & ~mask; } - - SCR scr3 = tc->readMiscReg(MISCREG_SCR_EL3); - HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); - bool have_el3 = ArmSystem::haveEL(tc, EL3); - - switch (el) - { - case EL0: - trapEL2 = (EL2Enabled(tc) && hcr.api == 0 && - (hcr.tge == 0 || hcr.e2h == 0)); - trapEL3 = have_el3 && scr3.api == 0; - break; - case EL1: - trapEL2 = EL2Enabled(tc) && hcr.api == 0; - trapEL3 = have_el3 && scr3.api == 0; - break; - case EL2: - trapEL2 = false; - trapEL3 = have_el3 && scr3.api == 0; - break; - case EL3: - trapEL2 = false; - trapEL3 = false; - break; - default: - // Unnaccessible - break; - } - if (trapEL2) - return trapPACUse(tc, EL2); - else if (trapEL3) - return trapPACUse(tc, EL3); - else - *out = ptr; - - return NoFault; } } // namespace gem5 diff --git a/src/arch/arm/pauth_helpers.hh b/src/arch/arm/pauth_helpers.hh index 11aec267b8..9316c962ed 100644 --- a/src/arch/arm/pauth_helpers.hh +++ b/src/arch/arm/pauth_helpers.hh @@ -1,5 +1,6 @@ // -*- mode:c++ -*- +// Copyright (c) 2020 ARM Limited // Copyright (c) 2020 Metempsy Technology Consulting // All rights reserved // @@ -113,15 +114,12 @@ namespace ArmISA Fault addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out); - // Strip() - // ======= - // Strip() returns a 64-bit value containing A, but replacing the + // stripPAC returns a 64-bit value containing A, but replacing the // pointer authentication code field bits with the extension of the // address bits. This can apply to either instructions or data, where, // as the use of tagged pointers is distinct, it might be // handled differently. - - Fault + void stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out); } // namespace ArmISA