arch,cpu: Make branching() a virtual member of PCStateBase.

Change-Id: I4422d07024e97dbd67e97ad95a16e1b06fd6be12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52066
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

src/arch/arm/pcstate.hh

@@ -196,7 +196,7 @@ class PCState : public GenericISA::UPCState<4>
     uint8_t size() const { return _size; }
 
     bool
-    branching() const
+    branching() const override
     {
         return ((this->pc() + this->size()) != this->npc());
     }

src/arch/generic/pcstate.hh

@@ -127,6 +127,7 @@ class PCStateBase : public Serializable
     }
 
     virtual void advance() = 0;
+    virtual bool branching() const = 0;
 
     void
     serialize(CheckpointOut &cp) const override
@@ -365,7 +366,7 @@ class SimplePCState : public PCStateCommon
     };
 
     bool
-    branching() const
+    branching() const override
     {
         return this->npc() != this->pc() + InstWidth;
     }
@@ -414,7 +415,7 @@ class UPCState : public SimplePCState<InstWidth>
     explicit UPCState(Addr val) { set(val); }
 
     bool
-    branching() const
+    branching() const override
     {
         return this->npc() != this->pc() + InstWidth ||
                this->nupc() != this->upc() + 1;
@@ -486,7 +487,7 @@ class DelaySlotPCState : public SimplePCState<InstWidth>
     explicit DelaySlotPCState(Addr val) { set(val); }
 
     bool
-    branching() const
+    branching() const override
     {
         return !(this->nnpc() == this->npc() + InstWidth &&
                  (this->npc() == this->pc() + InstWidth ||
@@ -559,7 +560,7 @@ class DelaySlotUPCState : public DelaySlotPCState<InstWidth>
     explicit DelaySlotUPCState(Addr val) { set(val); }
 
     bool
-    branching() const
+    branching() const override
     {
         return Base::branching() || this->nupc() != this->upc() + 1;
     }

src/arch/riscv/pcstate.hh

@@ -77,7 +77,7 @@ class PCState : public GenericISA::UPCState<4>
     bool rv32() const { return _rv32; }
 
     bool
-    branching() const
+    branching() const override
     {
         if (_compressed) {
             return npc() != pc() + 2 || nupc() != upc() + 1;

src/arch/x86/pcstate.hh

@@ -88,7 +88,7 @@ class PCState : public GenericISA::UPCState<8>
     void size(uint8_t newSize) { _size = newSize; }
 
     bool
-    branching() const
+    branching() const override
     {
         return (this->npc() != this->pc() + size()) ||
                (this->nupc() != this->upc() + 1);

src/cpu/o3/fetch.cc

@@ -1287,7 +1287,7 @@ Fetch::fetch(bool &status_change)
 
             // If we're branching after this instruction, quit fetching
             // from the same block.
-            predictedBranch |= this_pc.as<TheISA::PCState>().branching();
+            predictedBranch |= this_pc.branching();
             predictedBranch |= lookupAndUpdateNextPC(instruction, *next_pc);
             if (predictedBranch) {
                 DPRINTF(Fetch, "Branch detected with PC = %s\n", this_pc);

src/cpu/o3/iew.cc

@@ -461,8 +461,7 @@ IEW::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
             inst->seqNum < toCommit->squashedSeqNum[tid]) {
         toCommit->squash[tid] = true;
         toCommit->squashedSeqNum[tid] = inst->seqNum;
-        toCommit->branchTaken[tid] =
-            inst->pcState().as<TheISA::PCState>().branching();
+        toCommit->branchTaken[tid] = inst->pcState().branching();
 
         set(toCommit->pc[tid], inst->pcState());
         inst->staticInst->advancePC(*toCommit->pc[tid]);

src/cpu/simple/base.cc

@@ -461,8 +461,7 @@ BaseSimpleCPU::advancePC(const Fault &fault)
     SimpleExecContext &t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
 
-    const bool branching =
-        thread->pcState().as<TheISA::PCState>().branching();
+    const bool branching = thread->pcState().branching();
 
     //Since we're moving to a new pc, zero out the offset
     t_info.fetchOffset = 0;