In GCN3, the v_add_u32, v_sub_u32, and v_subrev_u32 instructions write
the carry-out value to VCC. VEGA introduces explicit carry-out versions
of these instructions (v_add_co_u32, v_sub_co_u32, and v_subrev_co_u32),
and modifies the behavior of the baseline, non-carry-out versions to not
write to VCC. Previously both the carry-out and non-carry-out versions
shared a single implementation that wrote to VCC. This patch correctly
implements the non-carry-out versions to avoid the VCC write.
This patch also makes the following substitutions for GCN3 instructions
that no longer exist in VEGA (this renaming has no functional impact):
v_addc_u32 -> v_addc_co_u32
v_subb_u32 -> v_subb_co_u32
v_subbrev_u32 -> v_subbrev_co_u32
Change-Id: I002fa6e9316d38fd4cc3554daff047523cfc12c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47240
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This introduces a new class and a new format for MD and
MDS form instructions where the shift amount, mask begin
and mask end are specified by two fields that must be
concatenated and adds the following instructions.
* Rotate Left Doubleword Immediate then Clear Left (rldicl[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Clear (rldic[.])
* Rotate Left Doubleword then Clear Left (rldcl[.])
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
Change-Id: Id7f1f24032242ccfdfda2f1aefd6fe9f0331f610
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40933
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers are being used, the rotation
operation changes for words. Instead of just rotating
the lower word of the operand, the lower word is first
duplicated in the upper word and then rotated. This
fixes the following instructions.
* Rotate Left Word Immediate then And with Mask (rlwinm[.])
* Rotate Left Word then And with Mask (rlwnm[.])
* Rotate Left Word Immediate then Mask Insert (rlwimi[.])
Change-Id: Ic743bceb8bafff461276984ecc999dedc1f94e9f
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40930
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This introduces a new class and a new format for XS form
instructions where the shift amount is specified by two
fields that must be concatenated and adds the following
instructions.
* Shift Left Doubleword (sld[.])
* Shift Right Doubleword (srd[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
* Extend-Sign Word and Shift Left Immediate (extswsli[.])
Change-Id: If51c676009ddafb40f855b66c00eeeffa5d8874c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40928
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers are being used, the instructions
must use only the lower word of the operand to be shifted.
This fixes the following instructions.
* Shift Left Word (slw[.])
* Shift Right Word (srw[.])
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
Change-Id: Ibc3124b9e3a8660b0ff9d0178218e34bcc028310
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40925
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This introduces new helpers for finding the count of
leading and trailing zero bits in a given value and adds
the following instructions.
* Count Trailing Zeros Word (cnttzw[.])
* Count Leading Zeros Doubleword (cntlzd[.])
* Count Trailing Zeros Doubleword (cnttzd[.])
Change-Id: I69dad34bc2cffb2ac70ecd3dba7301fa1cdcb340
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40920
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers are being used, the instructions
performing comparisons must use the entire 64 bits of the
register operands. Also, most of these instructions need
to determine the nature of the result if the Rc bit is set.
This fixes the following instructions.
* AND (and[.])
* OR (or[.])
* XOR (xor[.])
* NAND (nand[.])
* NOR (nor[.])
* Equivalent (eqv[.])
* AND with Complement (andc[.])
* OR with Complement (orc[.])
* Extend Sign Byte (extsb[.])
* Extend Sign Halfword (extsh[.])
* Count Leading Zeros Word (cntlzw[.])
* Compare Bytes (cmpb)
Change-Id: Ifecb0779fa6e2062d382f9abf8b2cfaf7cea3c96
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40917
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changes the base class for integer logical instructions
and adds a new class that is used to distinguish between
instructions using different operand types, i.e. register or
immediate. The formats have also been updated to make use of
the new base classes.
Change-Id: Id780cdb16405b01e82dcd22dc6e885ee15b716b2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40916
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers are being used, instead of always
performing a 32-bit comparison, these instructions must use
the L field to determine the type of comparison to be made.
The comparison can either be 32-bit or 64-bit. This fixes
the following instructions.
* Compare (cmp)
* Compare Logical (cmpl)
* Compare Immediate (cmpi)
* Compare Logical Immediate (cmpli)
Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40913
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.
Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40912
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40899
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.
Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40898
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: lkcl <luke.leighton@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.
Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40893
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Update in a pmp addr register can have effect on other
pmp rules, for example if TOR mode is used.
According to specs, update in a pmp entry is made using
an update to a pmpaddr reg, followed by an update to pmpcfg
reg which should be followed by sfence.vma. Currently,
in gem5 update in cfg register (combination of 8 pmpcfg
regs.), which should happen after a pmpaddr reg. update,
leads to an update in all pmp rules. However, there seems to
be a case where we receive an interrupt right before execution
of an instruction to update cfg register, which leads to unindented
side-effects of S mode addresses falsely falling into a wrong
pmp region. Updating pmp rules right after pmpaddr update, might
be redundant, but should not break anything otherwise.
Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47059
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
