arch-power: Refactor rotate instructions

This renames the mask span fields and the rotate helper
of the base class.

Change-Id: I120006a0c052fcc34eb154a68d4b7f70a464df65
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40929
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/power/insts/integer.cc

@@ -676,7 +676,7 @@ IntRotateOp::generateDisassembly(
     }
 
     // Print the shift, mask begin and mask end
-    ss << ", " << (int) sh << ", " << mb << ", " << me;
+    ss << ", " << (int) sh << ", " << (int) mb << ", " << (int) me;
 
     return ss.str();
 }

src/arch/power/insts/integer.hh

@@ -623,15 +623,17 @@ class IntConcatShiftOp : public IntOp
 
 
 /**
- * Class for integer rotate operations.
+ * Class for integer rotate operations with a shift amount obtained
+ * from a register or an immediate and the first and last bits of a
+ * mask obtained from immediates.
  */
 class IntRotateOp : public IntShiftOp
 {
   protected:
 
-    uint32_t mb;
-    uint32_t me;
     uint32_t fullMask;
+    uint8_t mb;
+    uint8_t me;
 
     /// Constructor
     IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass)
@@ -646,11 +648,11 @@ class IntRotateOp : public IntShiftOp
         }
     }
 
-    uint32_t
-    rotateValue(uint32_t rs, uint32_t shift) const
+    inline uint32_t
+    rotate(uint32_t value, uint32_t shift) const
     {
-        uint32_t n = shift & 31;
-        return (rs << n) | (rs >> (32 - n));
+        shift &= 31;
+        return (value << shift) | (value >> (32 - shift));
     }
 
     std::string generateDisassembly(

src/arch/power/isa/decoder.isa

@@ -195,10 +195,9 @@ decode PO default Unknown::unknown() {
     }
 
     format IntRotateOp {
-        20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
-                           (Ra & ~fullMask); }});
-        21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
-        23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
+        20: rlwimi({{ Ra = (rotate(Rs, sh) & fullMask) | (Ra & ~fullMask); }});
+        21: rlwinm({{ Ra = rotate(Rs, sh) & fullMask; }});
+        23: rlwnm({{ Ra = rotate(Rs, Rb) & fullMask; }});
     }
 
     format IntImmLogicOp {

src/arch/power/isa/formats/integer.isa

@@ -488,15 +488,17 @@ def format IntConcatShiftOp(code, computeCA = 0, inst_flags = []) {{
 }};
 
 
-// A special format for rotate instructions which use certain fields
-// from the instruction's binary encoding. We need two versions for each
-// instruction to deal with the Rc bit.
+// Integer instructions with or without immediate that perform rotate
+// operations. All instructions write to Ra and use Rs as a source
+// register. If immediate is not used, Rb is also used as a source
+// register. We need two versions for each instruction to deal with
+// the Rc bit.
 def format IntRotateOp(code, inst_flags = []) {{
 
     # The result is always in Ra
     dict = {'result':'Ra'}
 
-    # Setup the code for when Rc is set
+    # Code when Rc is set
     code_rc1 = readXERCode + code + computeCR0Code % dict
 
     # Generate the first class