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arch-power: Add fields for MD and MDS form instructions

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This introduces the extended opcode fields for MD and
MDS form instructions and the mb and me fields which
are concatenated with the MB and ME fields respectively
for specifying mask bounds for doubleword operands.

Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40932
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:22:07 +05:30
parent 59ae544eb3
commit ed99a79ca7
2 changed files with 4 additions and 0 deletions
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2
src/arch/power/isa/bitfields.isa
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@@ -38,6 +38,8 @@ def bitfield PO <31:26>;
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield DX_XO <5:1>;
def bitfield MD_XO <4:2>;
def bitfield MDS_XO <4:1>;
def bitfield VA_XO <5:0>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO <10:1>;

2
src/arch/power/types.hh
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@@ -49,7 +49,9 @@ BitUnion32(ExtMachInst)
Bitfield<15, 11> sh;
Bitfield<1> shn;
Bitfield<10, 6> mb;
Bitfield<5> mbn;
Bitfield< 5, 1> me;
Bitfield<5> men;
// Immediate fields
Bitfield<15, 0> si;