arch-power: Add sign-extend instructions

This adds the following instructions.
  * Extend Sign Word (extsw[.])

Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40919
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/power/insts/integer.cc

@@ -286,6 +286,7 @@ IntLogicOp::generateDisassembly(
         printSecondSrc = false;
     } else if (myMnemonic == "extsb" ||
                myMnemonic == "extsh" ||
+               myMnemonic == "extsw" ||
                myMnemonic == "cntlzw") {
         printSecondSrc = false;
     }

src/arch/power/isa/decoder.isa

@@ -579,6 +579,7 @@ decode PO default Unknown::unknown() {
         }
 
         983: StoreIndexOp::stfiwx({{ Mem = Fs_uw; }});
+        986: IntLogicOp::extsw({{ Ra = sext<32>(Rs); }}, true);
 
         // These instructions are of XO form with bit 21 as the OE bit.
         default: decode XO_XO {