diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 43ef2100c1..d7c8ed4f1b 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -286,6 +286,7 @@ IntLogicOp::generateDisassembly(
         printSecondSrc = false;
     } else if (myMnemonic == "extsb" ||
                myMnemonic == "extsh" ||
+               myMnemonic == "extsw" ||
                myMnemonic == "cntlzw") {
         printSecondSrc = false;
     }
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 40311faa18..0ec249e78e 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -579,6 +579,7 @@ decode PO default Unknown::unknown() {
         }
 
         983: StoreIndexOp::stfiwx({{ Mem = Fs_uw; }});
+        986: IntLogicOp::extsw({{ Ra = sext<32>(Rs); }}, true);
 
         // These instructions are of XO form with bit 21 as the OE bit.
         default: decode XO_XO {