arch-power: Add fields for XS form instructions

This introduces the extended opcode field for XS form
instructions and the sh field which is concatenated
with the SH field for specifying a shift amount for
doubleword operands.

Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40927
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/power/isa/bitfields.isa

@@ -44,6 +44,7 @@ def bitfield XFL_XO        <10:1>;
 def bitfield XFX_XO        <10:1>;
 def bitfield XL_XO         <10:1>;
 def bitfield XO_XO         <9:1>;
+def bitfield XS_XO         <10:2>;
 
 // Register fields
 def bitfield RA            <20:16>;

src/arch/power/types.hh

@@ -47,6 +47,7 @@ BitUnion32(ExtMachInst)
 
     // Shifts and masks
     Bitfield<15, 11> sh;
+    Bitfield<1>      shn;
     Bitfield<10,  6> mb;
     Bitfield< 5,  1> me;