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arch-power: Fix shift instructions

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Now that 64-bit registers are being used, the instructions
must use only the lower word of the operand to be shifted.
This fixes the following instructions.
  * Shift Left Word (slw[.])
  * Shift Right Word (srw[.])
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])

Change-Id: Ibc3124b9e3a8660b0ff9d0178218e34bcc028310
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40925
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:21:41 +05:30
parent 4b948e64bd
commit 16022594e5
1 changed files with 32 additions and 37 deletions
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69
src/arch/power/isa/decoder.isa
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@@ -241,11 +241,13 @@ decode PO default Unknown::unknown() {
}
24: IntShiftOp::slw({{
if (Rb & 0x20) {
Ra = 0;
} else {
Ra = Rs << (Rb & 0x1f);
int32_t shift = Rb_sw;
uint32_t res = Rs_uw & ~((shift << 26) >> 31);
if (shift != 0) {
shift = bits(shift, 4, 0);
res = res << shift;
}
Ra = res;
}});
format IntLogicOp {
@@ -500,11 +502,13 @@ decode PO default Unknown::unknown() {
}
536: IntShiftOp::srw({{
if (Rb & 0x20) {
Ra = 0;
} else {
Ra = Rs >> (Rb & 0x1f);
int32_t shift = Rb_sw;
uint32_t res = Rs_uw & ~((shift << 26) >> 31);
if (shift != 0) {
shift = bits(shift, 4, 0);
res = res >> shift;
}
Ra = res;
}});
538: IntLogicOp::cnttzw({{ Ra = findTrailingZeros(Rs_uw); }}, true);
@@ -588,45 +592,36 @@ decode PO default Unknown::unknown() {
format IntShiftOp {
792: sraw({{
int32_t s = Rs;
if (Rb == 0) {
Ra = Rs;
setCA = true;
} else if (Rb & 0x20) {
if (s < 0) {
Ra = (uint32_t)-1;
if (s & 0x7fffffff) {
setCA = true;
} else {
setCA = false;
}
} else {
Ra = 0;
setCA = false;
int32_t src = Rs_sw;
uint32_t shift = Rb_uw;
int64_t res;
if (bits(shift, 5)) {
res = src >> 31;
if (res != 0) {
setCA = true;
}
} else {
Ra = s >> (Rb & 0x1f);
if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
setCA = true;
if (shift != 0) {
shift = bits(shift, 4, 0);
res = src >> shift;
setCA = src < 0 && (src & mask(shift)) != 0;
} else {
setCA = false;
res = src;
}
}
Ra = res;
}}, true);
824: srawi({{
if (sh == 0) {
Ra = Rs;
setCA = false;
int32_t src = Rs_sw;
int64_t res;
if (sh) {
res = src >> sh;
setCA = src < 0 && (src & mask(sh)) != 0;
} else {
int32_t s = Rs;
Ra = s >> sh;
if (s < 0 && (s << (32 - sh)) != 0) {
setCA = true;
} else {
setCA = false;
}
res = src;
}
Ra = res;
}}, true);
}