arch-arm: Remove the TLB::flush overload for TLBI IPA

This will be handled by the MMU

Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45782
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/tlb.cc

@@ -451,15 +451,6 @@ TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
     }
 }
 
-void
-TLB::flush(const TLBIIPA &tlbi_op)
-{
-    assert(!isStage2);
-
-    // Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
-    stage2Tlb->flush(tlbi_op.makeStage2());
-}
-
 void
 TLB::drainResume()
 {

src/arch/arm/tlb.hh

@@ -66,7 +66,6 @@ class TLBIALLN;
 class TLBIMVA;
 class TLBIASID;
 class TLBIMVAA;
-class TLBIIPA;
 
 class TlbTestInterface
 {
@@ -294,12 +293,6 @@ class TLB : public BaseTLB
      */
     void flush(const TLBIMVAA &tlbi_op);
 
-    /**
-     * Invalidate all entries in the stage 2 TLB that match the given ipa
-     * and the current VMID
-     */
-    void flush(const TLBIIPA &tlbi_op);
-
     Fault trickBoxCheck(const RequestPtr &req, Mode mode,
                         TlbEntry::DomainType domain);
 

src/arch/arm/tlbi_op.cc

@@ -182,11 +182,11 @@ DTLBIMVA::operator()(ThreadContext* tc)
 void
 TLBIIPA::operator()(ThreadContext* tc)
 {
-    getMMUPtr(tc)->flush(*this);
+    getMMUPtr(tc)->flushStage2(makeStage2());
 
     CheckerCPU *checker = tc->getCheckerCpuPtr();
     if (checker) {
-        getMMUPtr(checker)->flush(*this);
+        getMMUPtr(checker)->flushStage2(makeStage2());
     }
 }
 

src/arch/arm/tlbi_op.hh

@@ -343,6 +343,12 @@ class TLBIIPA : public TLBIOp
 
     void operator()(ThreadContext* tc) override;
 
+    bool
+    stage1Flush() const override
+    {
+        return false;
+    }
+
     /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
     TLBIMVAA
     makeStage2() const