diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index d759819bc7..c8174b4a82 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -451,15 +451,6 @@ TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, } } -void -TLB::flush(const TLBIIPA &tlbi_op) -{ - assert(!isStage2); - - // Note, TLBIIPA::makeStage2 will generare a TLBIMVAA - stage2Tlb->flush(tlbi_op.makeStage2()); -} - void TLB::drainResume() { diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 3d96446d1e..b59fd67746 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -66,7 +66,6 @@ class TLBIALLN; class TLBIMVA; class TLBIASID; class TLBIMVAA; -class TLBIIPA; class TlbTestInterface { @@ -294,12 +293,6 @@ class TLB : public BaseTLB */ void flush(const TLBIMVAA &tlbi_op); - /** - * Invalidate all entries in the stage 2 TLB that match the given ipa - * and the current VMID - */ - void flush(const TLBIIPA &tlbi_op); - Fault trickBoxCheck(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain); diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc index 5bcc009d82..d918454c30 100644 --- a/src/arch/arm/tlbi_op.cc +++ b/src/arch/arm/tlbi_op.cc @@ -182,11 +182,11 @@ DTLBIMVA::operator()(ThreadContext* tc) void TLBIIPA::operator()(ThreadContext* tc) { - getMMUPtr(tc)->flush(*this); + getMMUPtr(tc)->flushStage2(makeStage2()); CheckerCPU *checker = tc->getCheckerCpuPtr(); if (checker) { - getMMUPtr(checker)->flush(*this); + getMMUPtr(checker)->flushStage2(makeStage2()); } } diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh index 924aabde38..e2f3eee2cd 100644 --- a/src/arch/arm/tlbi_op.hh +++ b/src/arch/arm/tlbi_op.hh @@ -343,6 +343,12 @@ class TLBIIPA : public TLBIOp void operator()(ThreadContext* tc) override; + bool + stage1Flush() const override + { + return false; + } + /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */ TLBIMVAA makeStage2() const