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arch-power: Add word modulo instructions

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This adds the following instructions.
  * Modulo Signed Word (modsw)
  * Modulo Unsigned Word (moduw)

Change-Id: Id84ff46d0114ab859bd8616d3dcf22111cf3bda2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40909
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:18:08 +05:30
parent 3d2bb88f62
commit bead9677a2
1 changed files with 22 additions and 0 deletions
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22
src/arch/power/isa/decoder.isa
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@@ -334,6 +334,17 @@ decode PO default Unknown::unknown() {
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
267: IntArithOp::moduw({{
uint64_t src1 = Ra_uw;
uint64_t src2 = Rb_uw;
if (src2 != 0) {
Rt = src1 % src2;
} else {
Rt = 0;
}
}});
278: MiscOp::dcbt({{ }});
279: LoadIndexOp::lhzx({{ Rt = Mem_uh; }});
284: IntLogicOp::eqv({{ Ra = ~(Rs ^ Rb); }});
@@ -435,6 +446,17 @@ decode PO default Unknown::unknown() {
}
759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
779: IntArithOp::modsw({{
int64_t src1 = Ra_sw;
int64_t src2 = Rb_sw;
if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
Rt = src1 % src2;
} else {
Rt = 0;
}
}});
790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
792: IntLogicOp::sraw({{