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arch-power: Add fields for VA form instructions

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This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40904
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:17:49 +05:30
committed by Boris Shingarov
parent 930419bcb2
commit a74a9633f2
2 changed files with 4 additions and 1 deletions
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2
src/arch/power/isa/bitfields.isa
View File

@@ -38,6 +38,7 @@ def bitfield PO <31:26>;
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield DX_XO <5:1>;
def bitfield VA_XO <5:0>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO <10:1>;
def bitfield XFX_XO <10:1>;
@@ -47,6 +48,7 @@ def bitfield XO_XO <9:1>;
// Register fields
def bitfield RA <20:16>;
def bitfield RB <15:11>;
def bitfield RC <10:6>;
def bitfield RS <25:21>;
def bitfield RT <25:21>;
def bitfield FRA <20:16>;

3
src/arch/power/isa/operands.isa
View File

@@ -44,7 +44,8 @@ def operands {{
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),