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arch-power: Add fields for DX form instructions

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This introduces the extended opcode field for DS form
instructions and the fields d0, d1 and d2 which are
concatenated for specifying a signed integer immediate
operand.

Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40901
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:17:38 +05:30
committed by Boris Shingarov
parent 8455995d09
commit b43aa16535
2 changed files with 4 additions and 0 deletions
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1
src/arch/power/isa/bitfields.isa
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@@ -37,6 +37,7 @@
def bitfield PO <31:26>;
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield DX_XO <5:1>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO <10:1>;
def bitfield XFX_XO <10:1>;

3
src/arch/power/types.hh
View File

@@ -55,6 +55,9 @@ BitUnion32(ExtMachInst)
Bitfield<15, 0> ui;
Bitfield<15, 0> d;
Bitfield<15, 2> ds;
Bitfield<15, 6> d0;
Bitfield<20, 16> d1;
Bitfield< 1, 0> d2;
// Special purpose register identifier
Bitfield<20, 11> spr;