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arch-power: Fix compare instructions

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Now that 64-bit registers are being used, instead of always
performing a 32-bit comparison, these instructions must use
the L field to determine the type of comparison to be made.
The comparison can either be 32-bit or 64-bit. This fixes
the following instructions.
  * Compare (cmp)
  * Compare Logical (cmpl)
  * Compare Immediate (cmpi)
  * Compare Logical Immediate (cmpli)

Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40913
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:19:40 +05:30
parent ef46e4d6a4
commit 7f6c7440e2
1 changed files with 16 additions and 4 deletions
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20
src/arch/power/isa/decoder.isa
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@@ -74,11 +74,17 @@ decode PO default Unknown::unknown() {
}
10: IntImmCompLogicOp::cmpli({{
cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so);
if (l)
cr = makeCRFieldUnsigned(Ra, ui, xer.so);
else
cr = makeCRFieldUnsigned((uint32_t) Ra, ui, xer.so);
}});
11: IntImmCompOp::cmpi({{
cr = makeCRFieldSigned(Ra_sw, si, xer.so);
if (l)
cr = makeCRFieldSigned(Ra, si, xer.so);
else
cr = makeCRFieldSigned((int32_t) Ra, si, xer.so);
}});
format IntImmArithOp {
@@ -218,7 +224,10 @@ decode PO default Unknown::unknown() {
31: decode X_XO {
0: IntCompOp::cmp({{
cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
if (l)
cr = makeCRFieldSigned(Ra, Rb, xer.so);
else
cr = makeCRFieldSigned((int32_t)Ra, (int32_t)Rb, xer.so);
}});
format LoadIndexOp {
@@ -245,7 +254,10 @@ decode PO default Unknown::unknown() {
}
32: IntCompOp::cmpl({{
cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
if (l)
cr = makeCRFieldUnsigned(Ra, Rb, xer.so);
else
cr = makeCRFieldUnsigned((uint32_t)Ra, (uint32_t)Rb, xer.so);
}});
52: LoadIndexOp::lbarx({{