Commit Graph

206 Commits

Author SHA1 Message Date
Gabe Black
c853187273 arch: Add a virtual method to the BaseISA to reset its ThreadContext.
This will be used as part of a generic CPU reset mechanism.

Change-Id: I010f6bdaca0cbb6be1799ccdc345c4828515209d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67572
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-02-03 06:17:11 +00:00
Daniel R. Carvalho
b2bf811aea misc: Remove the FreeBSD namespace
This namespace has gone through the deprecation period
and can now be removed.

Change-Id: Ic0c838709121278584a295ea19a8283d5765b9c9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67365
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-01-17 09:16:20 +00:00
Daniel R. Carvalho
d14cde6bd7 misc: Remove the Linux namespace
This namespace has gone through the deprecation period
and can now be removed.

Change-Id: I73d7792ab8897d00b143d82d0fb70987ca410438
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67364
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2023-01-17 09:16:20 +00:00
Giacomo Travaglini
336e732d54 misc: Replace namespace Trace with lowercase trace
This is what the coding style demands

Change-Id: Ida6a71ad9c2c02cccd584bbaf37a6da751c5b856
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63891
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2022-10-02 16:30:15 +00:00
Gabe Black
5d00ba897f arch: Make the (read|set)MiscReg methods virtual.
They will then be accessible through the base class. This adds some
small hypothetical amount of overhead to each call, but a quick test
booting linux on x86 does not show any significant slowdown.

Change-Id: If706ddf173d4e24d85468fb118b45099acf3c05b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51237
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-08-20 01:15:23 +00:00
Gabe Black
b3365e767a arch: Make the ISA::clear() method virtual.
This method is not at all on the critical path, and the adding virtual
method overhead to it will have essentially no effect on over all
performance.

Change-Id: I583bbe30f5ed923a0c771f36c3f07e5979c28476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51236
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-20 01:14:54 +00:00
Hoa Nguyen
35bb55554e arch: Bump MaxVecRegLenInBytes to 2^16
Per chapter 2 of RVV 1.0 specs [1], RISCV vector extension supports
vector register size of upto 64kB.

[1] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

Change-Id: Ib62eb9d59006403f6fe08cfb06cb8a1bc0adbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-08-19 02:48:36 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-03 09:10:41 +00:00
Gabe Black
70289e72cd arch,cpu: Store pointers to RegClass-es instead of instances.
This lets us put the actual RegClass-es somewhere else and give them
names.

Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49784
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
2022-07-26 19:37:59 +00:00
Gabe Black
274042a362 arch: Add an "as" template to dummy vec regs.
Keep the unit tests compiling until the generic dummy vec and vec pred
regs are unnecessary and are eliminated.

Change-Id: I65d99cd3f4c41e89834b71a8af90872d8d5a4590
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57749
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-16 15:02:44 +00:00
Gabe Black
f847b4a5e9 arch: Make the DummyVec... types the same size as RegVal.
This makes RegClass-es which don't specify a size work with the Dummy
types of VecRegContainer and VecPredRegContainer, and avoids having to
set up extra plumbing in ISAs that don't need it.

Change-Id: I059306a54b2a9cf7a22258a01e0821e370f0590a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56929
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2022-03-14 23:54:16 +00:00
Gabe Black
6d27a3bb50 cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
This simplifies and generalizes the ExecContext interface significantly.
This does *not* change the "Writeable" accessors for the vec and pred
registers, and it also ignores MiscRegs which have some different
semantics.

Change-Id: I8cb80da890fc8915f03be04e136662a257d06946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49114
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-19 20:23:51 +00:00
Gabe Black
5e1fdf7586 arch: Remove TheISA::VecElem from arch/vecregs.hh.
Also remove unnecessary includes from the x86 version, and fix up
transitive includes from other x86 files.

Change-Id: I9f7d330f287c9ed52eed1544c47251b4354cfab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49166
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 18:48:55 +00:00
Gabe Black
f4ee1a9536 arch: Get rid of the TheISA::NumVecElemPerVecReg variable.
Remove it from the arch/vecregs.hh interface. It's used internally by
ARM, where it will remain.

Change-Id: Ic319b404cbd77875c780faee66d5abdd7bfc0608
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49165
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 18:48:18 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject().
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
Gabe Black
25d36c81c9 arch,cpu: Turn the Decoder objects into SimObjects.
Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
3e766837b0 arch,cpu: Stop using TheISA::Decoder in most places.
The only places that still use that indirection are where the decoder
itself is instantiated with "new".

Also, add an "as" method which makes casting to an ISA specific decoder
type easier and less error prone.

Change-Id: Ib4a9cce7f96da2a9a8fe19113628694904893b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52079
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
3d52a0ea97 arch: Make the decoder decode() method virtual.
Change-Id: I60f0c4ffbd63069caaee190a78f007df79b61808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52078
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
ce60dc8d3a arch: Make the decoder moreBytes method virtual.
Change-Id: I9135508916de91172ec9649d59d80574ac2aaf16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52077
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
792745f4f0 arch: Make the decoder takeOverFrom method virtual.
This is only implemented for x86. It's called very rarely, and so
virtual function overhead is practically irrelevant.

Change-Id: Ib6e05a903df95b801164e44d1662e130419fdbd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52076
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
81fa62fc91 arch: Make the decoder reset() method virtual.
This is called very infrequently, and so it's virtual overhead is
practically irrelevant.

Change-Id: If92cd96f75234c65c4cdffe392c32cfdd9b0c8cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52074
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
5e7c964158 arch: Promote outOfBytes/needMoreBytes to the InstDecoder class.
Change-Id: Ie8f31e424081f002e3d74edd1685b4a977c545c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52073
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
29950b81ce arch: Promote instReady to the base InstDecoder class.
Move the instDone flag, and the instReady function which was
consistently implemented just to return it, to the base InstDecoder
class. This flag can still be accessed easily from the subclasses, but
now it can be retrieved with just an InstDecoder pointer without a
virtual function call.

Change-Id: I8c662aa01da8fe33ffe679071c701e0aadc1a795
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52072
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
7d00ef8c5b arch: Rename PCStateCommon to PCStateWithNext.
This intermediate class has a fairly vague name. This new name more
specifically describes what this PCState class adds to its base class.

Change-Id: I6d19383f3eb2895d924187ddbf8185352db71542
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52486
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
9f2fa6c4ce arch,cpu: Make branching() a virtual member of PCStateBase.
Change-Id: I4422d07024e97dbd67e97ad95a16e1b06fd6be12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52066
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
f8b8ab90ac arch: Make the advance() method virtual and in PCStateBase.
It's occasionally necessary to advance the PC to the next instruction
without having an instruction to do it with. This makes it available
without having to cast to a PCState subclass.

Change-Id: I3b7d94afdfb27b34279e58158782e87ab5066a37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52065
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
b1716fb8bd arch,cpu-minor: Make the uReset method virtual in PCStateBase.
This is used in the minor CPU, but maybe shouldn't. This makes it
accessible from a generic PCStatePtr without having to cast it to a
PCState subclass.

Change-Id: Ied89e2c9c69b1a7d647129fdade10312e21dcaa1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52064
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
Maintainer: ZHENGRONG WANG <seanyukigeek@gmail.com>
2021-11-30 23:30:06 +00:00
Gabe Black
8279191cd9 misc,cpu: Make ThreadContext work with PCStateBase-s.
Change-Id: I92f1d79c697bb45f610604c9e84b24ea93d58776
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52058
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-30 23:30:06 +00:00
Gabe Black
70f9a32117 cpu,arch: Eliminate the ThreadContext::nextInstAddr method.
This is no longer used.

Change-Id: I0ec170fb3b450430bbeff0a3c37bcdafe70c92b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52053
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
f784097f7a arch: Add a "set" function to set one PCState to another.
Most of the time, the type pointed to by a PCState pointer or reference
will be the same as all the others, if not nullptr.

This change adds a set of "set" functions which assume that the
underlying type of each pointer or reference are the same, and handles
casting, copying things over, creating a new copy, etc, for you. It uses
a new "update" virtual method on PCState subclasses which casts the
source to the same type as the destination and copies values over.

Note that the "set" function doesn't actually verify that the two types
are the same, just like the overloaded ==, != and << operators. In the
future, those checks can be added for debugging purposes, probably
guarded by a configuration variable which can be toggled on or off to
get better performance or more thorough error checking.

The main advantage of these wrappers are that they allows consistent
semantics whether your moving a value from a pointer, or from a yet
unconverted PCState subclass, or vice versa, which will be particularly
helpful while transitioning between using raw PCState instances and
using primarily pointers and references.

This change also adds wrappers which handle std::unique_ptr, which makes
it easier to use them as arguments to these functions. Otherwise, if the
std::unique_ptr is a temporary value, using the return value of .get()
will let the std::unique_ptr go out of scope, making it delete the data
pointed to by the returned pointed. By keeping the std::unique_ptr
around on the stack, that prevents it from going out of scope.

Change-Id: I2c737b08e0590a2c46e212a7b9efa543bdb81ad3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52041
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
3ecc9f8b66 arch: Add a newPCState method to the ISA class.
This method is the seed which creates a new PCState object of the
appropriate type. It can be used to initialize PCStateBase *s so that they
always point to something valid and can be manipulated without having to
first check if there's something there, as opposed to the alternative
where a pointer might be null until it's first pointed at something.

Change-Id: If06ee633846603acbfd2432f3d8bac6746a8b729
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-23 07:45:29 +00:00
Gabe Black
8de2e2ee77 arch: Virtualize printing a PCState.
Introduce a virtual output() method which prints the current PCState to
the given output stream, and define an overload for << to use that
method. This will make it possible to print a PCState without knowing
what the actual type is.

Change-Id: I663619b168c0b2b90c148b45ae16d77f03934e5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52039
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-23 07:45:29 +00:00
Gabe Black
e3a79d40f4 arch: Add a virtually backed PCState == operator.
Define a == operator and an equals() virtual method for the PCStateBase
class which it calls. The equals method will compare the owning PCState
instance with another instance of the same PCState class.

Change-Id: Ia704f1bc9e1217ce191671fe574c226ee1b73278
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52038
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
9df4025c23 arch: Promote the PC and microPC to the PCStateBase class.
Also move up the accessors for them. By putting the storage in the base
class, we can keep the accessors non-virtual and keep their overhead
low. Subclasses will be free to set those values to whatever they want
with no overhead, just as if they were natively part of that class.

Change-Id: I58e058def174e0bf591c0a9f050c23f61e9d8823
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52037
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-17 12:13:56 +00:00
Giacomo Travaglini
404077e8ff arch: Add vec_reg.test & vec_pred_reg.test unittests
Change-Id: Ieb85e0d35032585ead1e3b399f8eaf5dbc246d76
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44508
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-15 14:21:11 +00:00
Gabe Black
4b361aa4bc arch,cpu: Refactor PCState construction a little.
Make the Addr constructor explicit to avoid implicit/hidden conversions
from Addr.

Also, add a copy constructor to the PCState types, and explicitly enable
the assignment operator.

Change-Id: Ibef17ece7fd06b2f9709c46d118e88a80da0b194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52036
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
3f937352fa arch: Add a virtual clone() method to PCState.
This will let callers create a separate copy of a PCState class
instance. This makes it more explicit when creating copies of a PCState
to make sure the programmer is more aware, and avoids having to know
what the actual type is to make a copy.

Change-Id: I728a278afdb55b800c753a5b7f65f62f4a80c043
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52035
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
284f75b61e arch: Add some helpers to make it easier to cast PCState.
These helpers will make it easier to cast a PCStatePtr into an ISA
specific class with less syntactic fluff. They are currently implemented
with a static_cast for performance reasons, but could be implemented
with a dynamic_cast and an assert for extra debugging if you were
willing to pay the performance overhead. In the future this might be
switched/enabled as an extra debugging mode, like how locking can have
extra checks enabled in the Linux kernel.

Change-Id: Ibc2443c6b991ebc2e5d0240a88436849cb6de2b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52033
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-08 02:16:01 +00:00
Gabe Black
a5984cc497 arch: Extract PCStateCommon from PCStateBase.
This class has a lot of common functionality which all PCState classes
use, but in order to make it a true base class which provides the
complete interface for PCState-s throughout gem5, all its methods would
need to become virtual. That doesn't have to be the case today because
we use the literal full ISA specific PC class directly, but we need to
move away from that.

This change leaves PCStateBase empty, since we don't know what will need
to be accessible in base classes through a common/virtual interface.

Also, move methods which do not depend on the InstWidth template
parameter out of SimplePCState and into PCStateCommon. This avoids
having duplicate methods with the same contents which don't depend on
InstWidth.

Change-Id: I31309c4f35e897db1bc8318439fae1567a82b35e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52031
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-08 02:16:01 +00:00
Giacomo Travaglini
470939fa84 arch: Fix serialization/deserialization of Vector registers
This bug has been introduced by [1].
Without this fix a vector register is only partially unserialized, effectively
breaking checkpoiting for vectored applications. For example if I am
initializing a vector register with the following checkpointed value:

0xaaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa

The ParseParam logic will produce instead

0xaaaaaaaa_aaaaaaaa_00000000_00000000

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/41994

Change-Id: I5010d9f39d57fcee390e7419a64dbcd293e51fa0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51947
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-11-03 13:26:44 +00:00
Gabe Black
4fe56ff720 arch-arm,cpu: Replace rename modes with split reg/elem register files.
This simplifies the O3 CPU, and removes special cases around how vector
registers are handled. Now ARM is responsible for maintaining its
different register personalities internally.

Also, this re-establishes the invariant that registers are indexed as
complete, opaque entities with no internal structure, at least as far as
the CPU is concerned.

To make sure the KVM CPU sees the correct state, we need to sync over
the vector registers if we're in 32 bit mode when moving state to or
from gem5's ThreadContext.

Change-Id: I36416d609310ae0bc50c18809f5d9e19bfbb4d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-28 06:00:07 +00:00
Gabe Black
fbe002bf12 arch: Make the MMU ranged translateFunction pure virtual.
The (simple) implementation in each ISAs MMU can then specify the page
size it wants, which is the page size appropriate for that ISA.

Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50761
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-10-22 21:43:02 +00:00
Gabe Black
1f9fc43e72 arch: Add a MMUTranslationGen class to the BaseMMU.
This translation generator is returned by the new version of the
TranslateFunctional method which translates a region rather than a
single address. That method is currently virtual with a default
implementation which is not overloaded, but the plan is for the other
MMUs to override that method and inject their own page size minimally.
In the future, the MMUTranslationGen class and the implementations in
the MMUs may be updated so that they can, for instance, handle varying
page sizes across a single translation.

Change-Id: I39479f0f0e8150fc6e3e1a7097a0c8bd8d22d4e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50759
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 21:43:02 +00:00
Giacomo Travaglini
16253e494e arch: Fixed Packed register view for VecPredReg
A bug in the VecPredRegContainer::as method was introduced by
a past commit [1]. The commit was not properly handling the case of
a Packed representation

If Packed == true -> NumElement = NumBits instead of
NumElements = NumBits / sizeof(VecElem)

This patch is fixing it

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/42000

Change-Id: I308769c3938d0fac84316936f732a6c383146484
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51867
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 11:50:29 +00:00
Gabe Black
f1735afad3 misc: Include static_inst_fwd.hh in sim/faults.hh.
We only need a StaticInstPtr type, so we don't need to include all of
static_inst.hh. Also fix up some other files which were including some
other things transitively through sim/faults.hh.

Change-Id: I912a84963f33d99617f57d59517c402326f7a494
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50756
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-10-01 04:57:56 +00:00
Gabe Black
ede1ad4b8c arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.
Turn the functions within it into virtual methods on the ISA classes.
Eliminate the implementation in MIPS, which was just copy pasted from
Alpha long ago. Fix some minor style issues in ARM. Remove templating.
Switch from using an "XC" type parameter to using the ThreadContext *
installed in all ISA classes.

The ARM version of these functions actually depend on the ExecContext
delaying writes to MiscRegs to work correctly. More insiduously than
that, they also depend on the conicidental ThreadContext like
availability of certain functions like contextId and getCpuPtr which
come from the class which happened to implement the type passed into XC.

To accomodate that, those functions need both a real ThreadContext, and
another object which is either an ExecContext or a ThreadContext
depending on how the method is called.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1053

Change-Id: I68f95f7283f831776ba76bc5481bfffd18211bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50087
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-28 19:56:01 +00:00
Bobby R. Bruce
1853d57dc3 misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
This reverts commit a3f85217ab,
https://gem5-review.googlesource.com/c/public/gem5/+/48384

The reason for reverting this commit is it causes the Nightly build to
timeout: https://www.mail-archive.com/gem5-dev@gem5.org/msg40344.html

The exact cause of this failure was a stalling with the O3 processor on
ARM. The simulation reaches the following error and repeats until
timeout:

```
build/ARM/arch/arm/isa.cc:2634: warn: context 0: 2136500000 consecutive store conditional failures
```

The "realview-o3-ARM-x86_64-opt" test can replicate this:

```
./main.py run -j8 --uid
SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-o3-ARM-x86_64-opt
```

Change-Id: I9e9a20753c2a25c143e6a73f58716feb41861cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49927
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-04 04:37:49 +00:00
Gabe Black
a3f85217ab arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.
Turn the functions within it into virtual methods on the ISA classes.
Eliminate the implementation in MIPS, which was just copy pasted from
Alpha long ago. Fix some minor style issues in ARM. Remove templating.
Switch from using an "XC" type parameter to using the ThreadContext *
installed in all ISA classes.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1053

Change-Id: I19ee3a8fbe50a4d7907029c2dd2796d0e98e965f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48384
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-31 11:17:32 +00:00
Gabe Black
f183942ab8 cpu: Rename RegClassInfo to RegClass.
Change-Id: I0456462d5d306fc93a1fe160e45ff6b1b49f3c25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49103
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 20:04:51 +00:00
Giacomo Travaglini
242d0d467a arch: Implement operator& for TypeTLB
Change-Id: I05af52ba5e0ef84510ca3f4c27d8f9cd55e07d90
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48463
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00