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arch-arm,cpu: Replace rename modes with split reg/elem register files.

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This simplifies the O3 CPU, and removes special cases around how vector
registers are handled. Now ARM is responsible for maintaining its
different register personalities internally.

Also, this re-establishes the invariant that registers are indexed as
complete, opaque entities with no internal structure, at least as far as
the CPU is concerned.

To make sure the KVM CPU sees the correct state, we need to sync over
the vector registers if we're in 32 bit mode when moving state to or
from gem5's ThreadContext.

Change-Id: I36416d609310ae0bc50c18809f5d9e19bfbb4d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-09 18:02:00 -07:00
parent 25138cbb7a
commit 4fe56ff720
19 changed files with 76 additions and 374 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/ArmISA.py
View File

@@ -40,7 +40,6 @@ from m5.SimObject import SimObject
from m5.objects.ArmPMU import ArmPMU
from m5.objects.ArmSystem import SveVectorLength, ArmRelease
from m5.objects.BaseISA import BaseISA
from m5.objects.ISACommon import VecRegRenameMode
# Enum for DecoderFlavor
class DecoderFlavor(Enum): vals = ['Generic']

9
src/arch/arm/faults.cc
View File

@@ -494,6 +494,15 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// be handled in AArch64 mode (to64).
update(tc);
if (from64 != to64) {
// Switching modes, sync up versions of the vector register file.
if (from64) {
syncVecRegsToElems(tc);
} else {
syncVecElemsToRegs(tc);
}
}
if (to64) {
// Invoke exception handler in AArch64 state
invoke64(tc, inst);

27
src/arch/arm/isa.cc
View File

@@ -547,24 +547,6 @@ ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
setupThreadContext();
}
static void
copyVecRegs(ThreadContext *src, ThreadContext *dest)
{
auto src_mode = src->getIsaPtr()->vecRegRenameMode(src);
// The way vector registers are copied (VecReg vs VecElem) is relevant
// in the O3 model only.
if (src_mode == enums::Full) {
for (auto idx = 0; idx < NumVecRegs; idx++)
dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
} else {
for (auto idx = 0; idx < NumVecRegs; idx++)
for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
dest->setVecElemFlat(
idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
}
}
void
ISA::copyRegsFrom(ThreadContext *src)
{
@@ -577,7 +559,14 @@ ISA::copyRegsFrom(ThreadContext *src)
for (int i = 0; i < NUM_MISCREGS; i++)
tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
copyVecRegs(src, tc);
for (int i = 0; i < NumVecRegs; i++)
tc->setVecRegFlat(i, src->readVecRegFlat(i));
for (int i = 0; i < NumVecRegs; i++) {
for (int e = 0; e < NumVecElemPerVecReg; e++) {
tc->setVecElemFlat(i, e, src->readVecElemFlat(i, e));
}
}
// setMiscReg "with effect" will set the misc register mapping correctly.
// e.g. updateRegMap(val)

13
src/arch/arm/isa.hh
View File

@@ -52,7 +52,6 @@
#include "arch/generic/isa.hh"
#include "debug/Checkpoint.hh"
#include "enums/DecoderFlavor.hh"
#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
namespace gem5
@@ -884,18 +883,6 @@ namespace ArmISA
return gicv3CpuInterface != nullptr;
}
enums::VecRegRenameMode
initVecRegRenameMode() const override
{
return highestELIs64 ? enums::Full : enums::Elem;
}
enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const override
{
return _tc->pcState().aarch64() ? enums::Full : enums::Elem;
}
PARAMS(ArmISA);
ISA(const Params &p);

10
src/arch/arm/isa/insts/branch64.isa
View File

@@ -248,6 +248,16 @@ let {{
CondCodesV = new_cpsr.v;
NextAArch64 = !new_cpsr.width;
// Switch between aarch64 and aarch32, or vice versa.
if (new_cpsr.width != cpsr.width) {
if (new_cpsr.width) {
// Going to aarch32.
syncVecRegsToElems(xc->tcBase());
} else {
// Going to aarch64.
syncVecElemsToRegs(xc->tcBase());
}
}
NextItState = itState(new_cpsr);
NPC = purifyTaggedAddr(newPc, xc->tcBase(),
currEL(new_cpsr), true);

4
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -256,6 +256,8 @@ ArmV8KvmCPU::updateKvmState()
for (int i = 0; i < NUM_QREGS; ++i) {
KvmFPReg reg;
if (!inAArch64(tc))
syncVecElemsToRegs(tc);
auto v = tc->readVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
reg.s[j].i = v[j];
@@ -333,6 +335,8 @@ ArmV8KvmCPU::updateThreadContext()
auto v = tc->getWritableVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
v[j] = reg.s[j].i;
if (!inAArch64(tc))
syncVecRegsToElems(tc);
}
for (const auto &ri : getSysRegMap()) {

48
src/arch/generic/ISACommon.py
View File

@@ -1,48 +0,0 @@
# Copyright (c) 2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
class VecRegRenameMode(Enum):
'''Enum for Rename Mode in rename map
Elem: Each native-elem in a vector register is renamed independently.
Full: Vectors are renamed as one unit.'''
vals = ['Full', 'Elem']
__all__ = ['VecRegRenameMode']

1
src/arch/generic/SConscript
View File

@@ -45,7 +45,6 @@ SimObject('BaseInterrupts.py')
SimObject('BaseISA.py')
SimObject('BaseMMU.py')
SimObject('BaseTLB.py')
SimObject('ISACommon.py')
DebugFlag('PageTableWalker',
"Page table walker state machine debugging")

13
src/arch/generic/isa.hh
View File

@@ -43,7 +43,6 @@
#include <vector>
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/sim_object.hh"
@@ -74,18 +73,6 @@ class BaseISA : public SimObject
virtual bool inUserMode() const = 0;
virtual void copyRegsFrom(ThreadContext *src) = 0;
virtual enums::VecRegRenameMode
initVecRegRenameMode() const
{
return enums::Full;
}
virtual enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const
{
return initVecRegRenameMode();
}
const RegClasses &regClasses() const { return _regClasses; }
// Locked memory handling functions.

94
src/cpu/o3/cpu.cc
View File

@@ -87,16 +87,12 @@ CPU::CPU(const O3CPUParams &params)
iew(this, params),
commit(this, params),
/* It is mandatory that all SMT threads use the same renaming mode as
* they are sharing registers and rename */
vecMode(params.isa[0]->initVecRegRenameMode()),
regFile(params.numPhysIntRegs,
params.numPhysFloatRegs,
params.numPhysVecRegs,
params.numPhysVecPredRegs,
params.numPhysCCRegs,
params.isa[0]->regClasses(),
vecMode),
params.isa[0]->regClasses()),
freeList(name() + ".freelist", &regFile),
@@ -221,12 +217,8 @@ CPU::CPU(const O3CPUParams &params)
// Setup the rename map for whichever stages need it.
for (ThreadID tid = 0; tid < numThreads; tid++) {
isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
assert(isa[tid]);
assert(isa[tid]->initVecRegRenameMode() ==
isa[0]->initVecRegRenameMode());
commitRenameMap[tid].init(regClasses, &regFile, &freeList, vecMode);
renameMap[tid].init(regClasses, &regFile, &freeList, vecMode);
commitRenameMap[tid].init(regClasses, &regFile, &freeList);
renameMap[tid].init(regClasses, &regFile, &freeList);
}
// Initialize rename map to assign physical registers to the
@@ -249,29 +241,23 @@ CPU::CPU(const O3CPUParams &params)
RegId(FloatRegClass, ridx), phys_reg);
}
/* Here we need two 'interfaces' the 'whole register' and the
* 'register element'. At any point only one of them will be
* active. */
const size_t numVecs = regClasses.at(VecRegClass).size();
if (vecMode == enums::Full) {
/* Initialize the full-vector interface */
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
RegId rid = RegId(VecRegClass, ridx);
PhysRegIdPtr phys_reg = freeList.getVecReg();
renameMap[tid].setEntry(rid, phys_reg);
commitRenameMap[tid].setEntry(rid, phys_reg);
}
} else {
/* Initialize the vector-element interface */
const size_t numElems = regClasses.at(VecElemClass).size();
const size_t elemsPerVec = numElems / numVecs;
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
for (ElemIndex ldx = 0; ldx < elemsPerVec; ++ldx) {
RegId lrid = RegId(VecElemClass, ridx, ldx);
PhysRegIdPtr phys_elem = freeList.getVecElem();
renameMap[tid].setEntry(lrid, phys_elem);
commitRenameMap[tid].setEntry(lrid, phys_elem);
}
/* Initialize the full-vector interface */
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
RegId rid = RegId(VecRegClass, ridx);
PhysRegIdPtr phys_reg = freeList.getVecReg();
renameMap[tid].setEntry(rid, phys_reg);
commitRenameMap[tid].setEntry(rid, phys_reg);
}
/* Initialize the vector-element interface */
const size_t numElems = regClasses.at(VecElemClass).size();
const size_t elemsPerVec = numElems / numVecs;
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
for (ElemIndex ldx = 0; ldx < elemsPerVec; ++ldx) {
RegId lrid = RegId(VecElemClass, ridx, ldx);
PhysRegIdPtr phys_elem = freeList.getVecElem();
renameMap[tid].setEntry(lrid, phys_elem);
commitRenameMap[tid].setEntry(lrid, phys_elem);
}
}
@@ -831,48 +817,6 @@ CPU::removeThread(ThreadID tid)
*/
}
void
CPU::setVectorsAsReady(ThreadID tid)
{
const auto &regClasses = isa[tid]->regClasses();
const size_t numVecs = regClasses.at(VecRegClass).size();
if (vecMode == enums::Elem) {
const size_t numElems = regClasses.at(VecElemClass).size();
const size_t elemsPerVec = numElems / numVecs;
for (auto v = 0; v < numVecs; v++) {
for (auto e = 0; e < elemsPerVec; e++) {
scoreboard.setReg(commitRenameMap[tid].lookup(
RegId(VecElemClass, v, e)));
}
}
} else if (vecMode == enums::Full) {
for (auto v = 0; v < numVecs; v++) {
scoreboard.setReg(commitRenameMap[tid].lookup(
RegId(VecRegClass, v)));
}
}
}
void
CPU::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
{
auto pc = pcState(tid);
// new_mode is the new vector renaming mode
auto new_mode = isa[tid]->vecRegRenameMode(thread[tid]->getTC());
// We update vecMode only if there has been a change
if (new_mode != vecMode) {
vecMode = new_mode;
renameMap[tid].switchMode(vecMode);
commitRenameMap[tid].switchMode(vecMode);
renameMap[tid].switchFreeList(freelist);
setVectorsAsReady(tid);
}
}
Fault
CPU::getInterrupts()
{

27
src/cpu/o3/cpu.hh
View File

@@ -284,20 +284,6 @@ class CPU : public BaseCPU
/** Traps to handle given fault. */
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
/**
* Mark vector fields in scoreboard as ready right after switching
* vector mode, since software may read vectors at this time.
*/
void setVectorsAsReady(ThreadID tid);
/** Check if a change in renaming is needed for vector registers.
* The vecMode variable is updated and propagated to rename maps.
*
* @param tid ThreadID
* @param freelist list of free registers
*/
void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
@@ -336,16 +322,6 @@ class CPU : public BaseCPU
*/
TheISA::VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
/** Returns current vector renaming mode */
enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
/** Sets the current vector renaming mode */
void
vecRenameMode(enums::VecRegRenameMode vec_mode)
{
vecMode = vec_mode;
}
RegVal readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
@@ -500,9 +476,6 @@ class CPU : public BaseCPU
/** The commit stage. */
Commit commit;
/** The rename mode of the vector registers */
enums::VecRegRenameMode vecMode;
/** The register file. */
PhysRegFile regFile;

27
src/cpu/o3/regfile.cc
View File

@@ -54,11 +54,11 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalVecRegs,
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses &regClasses,
VecMode vmode)
const BaseISA::RegClasses &regClasses)
: intRegFile(_numPhysicalIntRegs),
floatRegFile(_numPhysicalFloatRegs),
vectorRegFile(_numPhysicalVecRegs),
vectorElemRegFile(_numPhysicalVecRegs * TheISA::NumVecElemPerVecReg),
vecPredRegFile(_numPhysicalVecPredRegs),
ccRegFile(_numPhysicalCCRegs),
numPhysicalIntRegs(_numPhysicalIntRegs),
@@ -73,8 +73,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
+ _numPhysicalVecRegs
+ _numPhysicalVecRegs * TheISA::NumVecElemPerVecReg
+ _numPhysicalVecPredRegs
+ _numPhysicalCCRegs),
vecMode(vmode)
+ _numPhysicalCCRegs)
{
RegIndex phys_reg;
RegIndex flat_reg_idx = 0;
@@ -160,13 +159,8 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
elemIdx].elemIndex() == elemIdx);
}
}
/* depending on the mode we add the vector registers as whole units or
* as different elements. */
if (vecMode == enums::Full)
freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
else
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
// The next batch of the registers are the predicate physical
// registers; put them onto the predicate free list.
@@ -183,17 +177,6 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
}
PhysRegFile::IdRange
PhysRegFile::getRegElemIds(PhysRegIdPtr reg)
{
panic_if(!reg->is(VecRegClass),
"Trying to get elems of a %s register", reg->className());
auto idx = reg->index();
return std::make_pair(
vecElemIds.begin() + idx * TheISA::NumVecElemPerVecReg,
vecElemIds.begin() + (idx+1) * TheISA::NumVecElemPerVecReg);
}
PhysRegFile::IdRange
PhysRegFile::getRegIds(RegClassType cls)
{

25
src/cpu/o3/regfile.hh
View File

@@ -50,7 +50,6 @@
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "debug/IEW.hh"
#include "enums/VecRegRenameMode.hh"
namespace gem5
{
@@ -68,7 +67,6 @@ class PhysRegFile
private:
using PhysIds = std::vector<PhysRegId>;
using VecMode = enums::VecRegRenameMode;
public:
using IdRange = std::pair<PhysIds::iterator,
PhysIds::iterator>;
@@ -85,6 +83,9 @@ class PhysRegFile
/** Vector register file. */
std::vector<TheISA::VecRegContainer> vectorRegFile;
std::vector<PhysRegId> vecRegIds;
/** Vector element register file. */
std::vector<RegVal> vectorElemRegFile;
std::vector<PhysRegId> vecElemIds;
/** Predicate register file. */
@@ -131,9 +132,6 @@ class PhysRegFile
/** Total number of physical registers. */
unsigned totalNumRegs;
/** Mode in which vector registers are addressed. */
VecMode vecMode;
public:
/**
* Constructs a physical register file with the specified amount of
@@ -144,9 +142,7 @@ class PhysRegFile
unsigned _numPhysicalVecRegs,
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses &regClasses,
VecMode vmode
);
const BaseISA::RegClasses &regClasses);
/**
* Destructor to free resources
@@ -230,11 +226,10 @@ class PhysRegFile
readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->is(VecElemClass));
auto ret = vectorRegFile[phys_reg->index()].as<TheISA::VecElem>();
RegVal val = ret[phys_reg->elemIndex()];
RegVal val = vectorElemRegFile[phys_reg->flatIndex()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
" has data %#x\n", phys_reg->elemIndex(),
int(phys_reg->index()), val);
phys_reg->index(), val);
return val;
}
@@ -318,8 +313,7 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
" %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
vectorRegFile[phys_reg->index()].as<TheISA::VecElem>()[
phys_reg->elemIndex()] = val;
vectorElemRegFile[phys_reg->flatIndex()] = val;
}
/** Sets a predicate register to the given value. */
@@ -347,11 +341,6 @@ class PhysRegFile
ccRegFile[phys_reg->index()] = val;
}
/** Get the PhysRegIds of the elems of a vector register.
* Auxiliary function to transition from Full vector mode to Elem mode.
*/
IdRange getRegElemIds(PhysRegIdPtr reg);
/**
* Get the PhysRegIds of the elems of all vector registers.
* Auxiliary function to transition from Full vector mode to Elem mode

6
src/cpu/o3/rename.cc
View File

@@ -955,9 +955,6 @@ Rename::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
++stats.undoneMaps;
}
// Check if we need to change vector renaming mode after squashing
cpu->switchRenameMode(tid, freeList);
}
void
@@ -1250,7 +1247,7 @@ Rename::readFreeEntries(ThreadID tid)
}
DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, "
"Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
"Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i %i)\n",
tid,
freeEntries[tid].iqEntries,
freeEntries[tid].robEntries,
@@ -1260,6 +1257,7 @@ Rename::readFreeEntries(ThreadID tid)
renameMap[tid]->numFreeIntEntries(),
renameMap[tid]->numFreeFloatEntries(),
renameMap[tid]->numFreeVecEntries(),
renameMap[tid]->numFreeVecElemEntries(),
renameMap[tid]->numFreePredEntries(),
renameMap[tid]->numFreeCCEntries());

98
src/cpu/o3/rename_map.cc
View File

@@ -110,10 +110,9 @@ SimpleRenameMap::rename(const RegId& arch_reg)
void
UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode)
PhysRegFile *_regFile, UnifiedFreeList *freeList)
{
regFile = _regFile;
vecMode = _mode;
intMap.init(regClasses.at(IntRegClass), &(freeList->intList));
floatMap.init(regClasses.at(FloatRegClass), &(freeList->floatList));
@@ -121,101 +120,6 @@ UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
vecElemMap.init(regClasses.at(VecElemClass), &(freeList->vecElemList));
predMap.init(regClasses.at(VecPredRegClass), &(freeList->predList));
ccMap.init(regClasses.at(CCRegClass), &(freeList->ccList));
}
void
UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
{
if (vecMode == enums::Elem) {
/* The free list should currently be tracking full registers. */
panic_if(freeList->hasFreeVecElems(),
"The free list is already tracking Vec elems");
panic_if(freeList->numFreeVecRegs() !=
regFile->numVecPhysRegs() - vecMap.numArchRegs(),
"The free list has lost vector registers");
/* Split the free regs. */
while (freeList->hasFreeVecRegs()) {
auto vr = freeList->getVecReg();
auto range = this->regFile->getRegElemIds(vr);
freeList->addRegs(range.first, range.second);
}
} else if (vecMode == enums::Full) {
/* The free list should currently be tracking register elems. */
panic_if(freeList->hasFreeVecRegs(),
"The free list is already tracking full Vec");
panic_if(freeList->numFreeVecElems() !=
regFile->numVecElemPhysRegs() - vecElemMap.numArchRegs(),
"The free list has lost vector register elements");
auto range = regFile->getRegIds(VecRegClass);
freeList->addRegs(range.first + vecMap.numArchRegs(), range.second);
/* We remove the elems from the free list. */
while (freeList->hasFreeVecElems())
freeList->getVecElem();
}
}
void
UnifiedRenameMap::switchMode(VecMode newVecMode)
{
if (newVecMode == enums::Elem && vecMode == enums::Full) {
/* Switch to vector element rename mode. */
vecMode = enums::Elem;
/* Split the mapping of each arch reg. */
int vec_idx = 0;
for (auto &vec: vecMap) {
PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
auto idx = 0;
for (auto phys_elem = range.first;
phys_elem < range.second; idx++, phys_elem++) {
setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
}
vec_idx++;
}
} else if (newVecMode == enums::Full && vecMode == enums::Elem) {
/* Switch to full vector register rename mode. */
vecMode = enums::Full;
/* To rebuild the arch regs we take the easy road:
* 1.- Stitch the elems together into vectors.
* 2.- Replace the contents of the register file with the vectors
* 3.- Set the remaining registers as free
*/
TheISA::VecRegContainer new_RF[vecMap.numArchRegs()];
const size_t numVecs = vecMap.numArchRegs();
const size_t numElems = vecElemMap.numArchRegs();
const size_t elemsPerVec = numElems / numVecs;
for (uint32_t i = 0; i < numVecs; i++) {
TheISA::VecElem *dst = new_RF[i].as<TheISA::VecElem>();
for (uint32_t l = 0; l < elemsPerVec; l++) {
RegId s_rid(VecElemClass, i, l);
PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
dst[l] = regFile->readVecElem(s_prid);
}
}
for (uint32_t i = 0; i < numVecs; i++) {
PhysRegId pregId(VecRegClass, i, 0);
regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
}
auto range = regFile->getRegIds(VecRegClass);
for (uint32_t i = 0; i < numVecs; i++) {
setEntry(RegId(VecRegClass, i), &(*(range.first + i)));
}
}
}
} // namespace o3

37
src/cpu/o3/rename_map.hh
View File

@@ -50,7 +50,6 @@
#include "cpu/o3/free_list.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"
namespace gem5
{
@@ -192,9 +191,6 @@ class UnifiedRenameMap
/** The predicate register rename map */
SimpleRenameMap predMap;
using VecMode = enums::VecRegRenameMode;
VecMode vecMode;
/**
* The register file object is used only to get PhysRegIdPtr
* on MiscRegs, as they are stored in it.
@@ -213,7 +209,7 @@ class UnifiedRenameMap
/** Initializes rename map with given parameters. */
void init(const BaseISA::RegClasses &regClasses,
PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode);
PhysRegFile *_regFile, UnifiedFreeList *freeList);
/**
* Tell rename map to get a new free physical register to remap
@@ -232,10 +228,8 @@ class UnifiedRenameMap
case FloatRegClass:
return floatMap.rename(arch_reg);
case VecRegClass:
assert(vecMode == enums::Full);
return vecMap.rename(arch_reg);
case VecElemClass:
assert(vecMode == enums::Elem);
return vecElemMap.rename(arch_reg);
case VecPredRegClass:
return predMap.rename(arch_reg);
@@ -274,11 +268,9 @@ class UnifiedRenameMap
return floatMap.lookup(arch_reg);
case VecRegClass:
assert(vecMode == enums::Full);
return vecMap.lookup(arch_reg);
case VecElemClass:
assert(vecMode == enums::Elem);
return vecElemMap.lookup(arch_reg);
case VecPredRegClass:
@@ -318,11 +310,9 @@ class UnifiedRenameMap
return floatMap.setEntry(arch_reg, phys_reg);
case VecRegClass:
assert(vecMode == enums::Full);
return vecMap.setEntry(arch_reg, phys_reg);
case VecElemClass:
assert(vecMode == enums::Elem);
return vecElemMap.setEntry(arch_reg, phys_reg);
case VecPredRegClass:
@@ -356,19 +346,18 @@ class UnifiedRenameMap
{
return std::min({intMap.numFreeEntries(),
floatMap.numFreeEntries(),
vecMode == enums::Full ? vecMap.numFreeEntries() :
vecElemMap.numFreeEntries(),
vecMap.numFreeEntries(),
vecElemMap.numFreeEntries(),
predMap.numFreeEntries()});
}
unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
unsigned numFreeVecEntries() const { return vecMap.numFreeEntries(); }
unsigned
numFreeVecEntries() const
numFreeVecElemEntries() const
{
return vecMode == enums::Full
? vecMap.numFreeEntries()
: vecElemMap.numFreeEntries();
return vecElemMap.numFreeEntries();
}
unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
@@ -388,20 +377,6 @@ class UnifiedRenameMap
vecPredRegs <= predMap.numFreeEntries() &&
ccRegs <= ccMap.numFreeEntries();
}
/**
* Set vector mode to Full or Elem.
* Ignore 'silent' modifications.
*
* @param newVecMode new vector renaming mode
*/
void switchMode(VecMode newVecMode);
/**
* Switch freeList of registers from Full to Elem or vicevers
* depending on vecMode (vector renaming mode).
*/
void switchFreeList(UnifiedFreeList* freeList);
};
} // namespace o3

3
src/cpu/o3/thread_context.cc
View File

@@ -137,9 +137,6 @@ ThreadContext::readLastSuspend()
void
ThreadContext::copyArchRegs(gem5::ThreadContext *tc)
{
// Set vector renaming mode before copying registers
cpu->vecRenameMode(tc->getIsaPtr()->vecRegRenameMode(tc));
// Prevent squashing
thread->noSquashFromTC = true;
getIsaPtr()->copyRegsFrom(tc);

1
src/cpu/simple_thread.cc
View File

@@ -80,6 +80,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
intRegs.resize(regClasses.at(IntRegClass).size());
floatRegs.resize(regClasses.at(FloatRegClass).size());
vecRegs.resize(regClasses.at(VecRegClass).size());
vecElemRegs.resize(regClasses.at(VecElemClass).size());
vecPredRegs.resize(regClasses.at(VecPredRegClass).size());
ccRegs.resize(regClasses.at(CCRegClass).size());
clearArchRegs();

6
src/cpu/simple_thread.hh
View File

@@ -100,6 +100,7 @@ class SimpleThread : public ThreadState, public ThreadContext
std::vector<RegVal> floatRegs;
std::vector<RegVal> intRegs;
std::vector<TheISA::VecRegContainer> vecRegs;
std::vector<RegVal> vecElemRegs;
std::vector<TheISA::VecPredRegContainer> vecPredRegs;
std::vector<RegVal> ccRegs;
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -253,6 +254,7 @@ class SimpleThread : public ThreadState, public ThreadContext
std::fill(floatRegs.begin(), floatRegs.end(), 0);
for (auto &vec_reg: vecRegs)
vec_reg.zero();
std::fill(vecElemRegs.begin(), vecElemRegs.end(), 0);
for (auto &pred_reg: vecPredRegs)
pred_reg.reset();
std::fill(ccRegs.begin(), ccRegs.end(), 0);
@@ -522,14 +524,14 @@ class SimpleThread : public ThreadState, public ThreadContext
RegVal
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
return vecElemRegs[reg * TheISA::NumVecElemPerVecReg + elemIndex];
}
void
setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
RegVal val) override
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
vecElemRegs[reg * TheISA::NumVecElemPerVecReg + elemIndex] = val;
}
const TheISA::VecPredRegContainer &