Hoa Nguyen 35bb55554e arch: Bump MaxVecRegLenInBytes to 2^16 ...

Per chapter 2 of RVV 1.0 specs [1], RISCV vector extension supports
vector register size of upto 64kB.

[1] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

Change-Id: Ib62eb9d59006403f6fe08cfb06cb8a1bc0adbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

2022-08-19 02:48:36 +00:00

..

freebsd

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

linux

misc: Stop using getVirtProxy.

2021-07-23 03:42:17 +00:00

BaseInterrupts.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

BaseISA.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

BaseMMU.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

BaseTLB.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

debugfaults.hh

misc,cpu: Make ThreadContext work with PCStateBase-s.

2021-11-30 23:30:06 +00:00

decode_cache.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

decoder.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

decoder.hh

arch,cpu: Turn the Decoder objects into SimObjects.

2021-12-06 03:09:22 +00:00

htm.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

htm.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

InstDecoder.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

interrupts.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa.hh

arch,cpu: Store pointers to RegClass-es instead of instances.

2022-07-26 19:37:59 +00:00

memhelpers.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

mmu.cc

arch: Make the MMU ranged translateFunction pure virtual.

2021-10-22 21:43:02 +00:00

mmu.hh

arch: Make the MMU ranged translateFunction pure virtual.

2021-10-22 21:43:02 +00:00

pcstate.hh

arch: Rename PCStateCommon to PCStateWithNext.

2021-11-30 23:30:06 +00:00

SConscript

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

tlb.hh

arch: Implement operator& for TypeTLB

2021-08-05 08:26:33 +00:00

vec_pred_reg.hh

arch: Add an "as" template to dummy vec regs.

2022-03-16 15:02:44 +00:00

vec_pred_reg.test.cc

arch: Add vec_reg.test & vec_pred_reg.test unittests

2021-11-15 14:21:11 +00:00

vec_reg.hh

arch: Bump MaxVecRegLenInBytes to 2^16

2022-08-19 02:48:36 +00:00

vec_reg.test.cc

arch: Add vec_reg.test & vec_pred_reg.test unittests

2021-11-15 14:21:11 +00:00