arch: Implement operator& for TypeTLB

Change-Id: I05af52ba5e0ef84510ca3f4c27d8f9cd55e07d90
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48463
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/generic/BaseTLB.py

@@ -45,6 +45,13 @@ class TypeTLB(ScopedEnum):
     instruction: TLB contains instruction entries only
     data: TLB contains data entries only
     unified: TLB contains both instruction and data entries
+
+    The enum values have been selected in order to perform bitwise
+    operations on them. For example a unified TLB contains both
+    instruction and data entries so code trying to assess if the
+    TLB is storing (e.g.) data entries can do that with:
+
+    bool has_data = tlb->type() & TypeTLB::data;
     """
     map = {
         'instruction' : 0x1,

src/arch/generic/tlb.hh

@@ -41,6 +41,8 @@
 #ifndef __ARCH_GENERIC_TLB_HH__
 #define __ARCH_GENERIC_TLB_HH__
 
+#include <type_traits>
+
 #include "arch/generic/mmu.hh"
 #include "base/logging.hh"
 #include "enums/TypeTLB.hh"
@@ -125,6 +127,21 @@ class BaseTLB : public SimObject
     BaseTLB* nextLevel() const { return _nextLevel; }
 };
 
+/** Implementing the "&" bitwise operator for TypeTLB allows us to handle
+ * TypeTLB::unified efficiently. For example if I want to check if a TLB
+ * is storing instruction entries I can do this with:
+ *
+ * tlb->type() & TypeTLB::instruction
+ *
+ * which will cover both TypeTLB::instruction and TypeTLB::unified TLBs
+ */
+inline auto
+operator&(TypeTLB lhs, TypeTLB rhs)
+{
+    using T = std::underlying_type_t<TypeTLB>;
+    return static_cast<T>(lhs) & static_cast<T>(rhs);
+}
+
 } // namespace gem5
 
 #endif // __ARCH_GENERIC_TLB_HH__