Last fixes

.gitignore

@@ -35,3 +35,4 @@ assembler/test.map
 ### test program files
 *.ram
 *.map
+Vivado

assembler/Makefile

@@ -11,7 +11,7 @@ IDIR=inc
 ODIR=obj
 SDIR=src
 
-CFLAGS = -Wall
+CFLAGS = -fcommon -Wall
 
 _DEPS = command.h files.h labels.h
 DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

programming_languages

@@ -0,0 +1,4 @@
+Rust
+C++
+C
+

programs/assignment2code.prog

@@ -0,0 +1,86 @@
+reset:
+    br always >main
+    nop
+hardfault:
+    reti
+    nop
+memfault:
+    reti
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+base_prescaler: .word 0x1
+
+main:
+    ldr r0,>led_addr    //LED addr
+    addi r6,8        //outer counter top
+    clr r7            //wait counter
+    ldr r8,>base_prescaler
+
+out_loop:
+    clr r1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+fill:
+    lsh r1,r1,1
+    addi r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+    addi r5,1
+    cmp neq r5,r6
+    br true >fill
+    nop
+    clr r5
+
+flush:
+    lsh r1,r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+    addi r5,1
+    cmp neq r5,r6
+    br true >flush
+    nop
+    clr r5
+    br always >out_loop
+    nop
+
+wait_prescaled:
+    // Load value from the switches
+    ldr r11,  >switches_addr
+    ld32 r9, r11
+    addi r9, 1
+
+    clr r11
+    add r11, r13, r11 // save link register
+
+    clr r10
+inc_j:
+    call >wait
+    cmp neq r10,r9
+    br true >inc_j
+    addi r10,1
+
+    clr r13
+    add r13, r13, r11 // restore link register
+
+    ret
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

programs/assignment2isr.prog

@@ -0,0 +1,96 @@
+reset:
+    br always >main
+    nop
+hardfault:
+    reti
+    nop
+memfault:
+    reti
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FF
+base_prescaler: .word 0x1
+priority_mask: .word 0xFFFFFF03
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    ldr r0,>led_addr    //LED addr
+    addi r6,8        //outer counter top
+    clr r7            //wait counter
+    ldr r8,>base_prescaler
+
+out_loop:
+    clr r1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+fill:
+    lsh r1,r1,1
+    addi r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+    addi r5,1
+    cmp neq r5,r6
+    br true >fill
+    nop
+    clr r5
+
+flush:
+    lsh r1,r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+    addi r5,1
+    cmp neq r5,r6
+    br true >flush
+    nop
+    clr r5
+    br always >out_loop
+    nop
+
+wait_prescaled:
+    // Load value from the switches
+    ldr r11,  >switches_addr
+    ld32 r9, r11
+    addi r9, 1
+
+    clr r11
+    add r11, r13, r11 // save link register
+
+    clr r10
+inc_j:
+    call >wait
+    cmp neq r10,r9
+    br true >inc_j
+    addi r10,1
+
+    clr r13
+    add r13, r13, r11 // restore link register
+
+    ret
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

programs/assignment2isr_.prog

@@ -0,0 +1,120 @@
+reset:
+br always >main
+nop
+
+hardfault:
+reti
+nop
+
+memfault:
+reti
+nop
+
+irq3:      
+br always >irq3_handler
+nop
+
+.align
+addr:
+.word 0x000F0000
+addrsw:
+.word 0x000F0006
+//w_cnt_top:	.word 0x1FC000
+w_cnt_top:	.word 0x1		//for simulation only
+
+// Constant Declaration
+.align
+sp_init:   .word 0x400 // Stackpointer Initial Value
+
+
+main:
+ldr r12, >sp_init
+clr r14
+ldr r0,>addr	//LED addr
+ldr r2,>addrsw	//sw addr
+addi r6,8		//outer counter top
+clr r7			//wait counter
+
+here:
+nop
+nop
+nop
+br always >here
+nop
+
+out_loop:
+ldr r8,>w_cnt_top
+clr r1
+st08 r0,r1
+call >wait
+nop
+
+fill:
+	lsh r1,r1,1
+	addi r1,1
+	st08 r0,r1
+	call >wait
+	nop
+
+	addi r5,1
+	cmp neq r5,r6
+	br true >fill
+	nop
+	clr r5
+
+flush:
+	lsh r1,r1,1
+	st08 r0,r1
+	call >wait
+	nop
+
+	addi r5,1
+	cmp neq r5,r6
+	br true >flush
+	nop
+	clr r5
+	br always >out_loop
+	nop
+
+//subroutine to iterate until counter overflow
+wait:
+	clr r3
+	ld16 r3,r2 //loading switches content to r3 from r2 address	
+	clr r9
+	clr r10
+	clr r11
+	br always >nfound
+	nop
+found:	rsh r8,r8,1 //one found
+nfound:	clr r4
+	addi r4,1
+	addi r10,1 //loop counter max 16
+	and r9,r3,r4
+	cmp eq r9,r4
+	br true >found
+	rsh r3,r3,1
+	clr r4
+	addi r4,16
+	cmp le r10,r4
+	br true >nfound
+	nop
+
+	clr r7				//inititalize inner counter
+	inc_i:
+	cmp neq r7,r8
+	br true >inc_i		//if i=cnt_top
+	addi r7,1
+	ret					//else
+	nop
+
+
+
+irq3_handler: 
+
+
+
+
+
+br always >out_loop
+nop
+reti

programs/blinky.prog

@@ -11,8 +11,8 @@ nop
 .align
 addr:
 .word 0x000F0000
-w_cnt_top:	.word 0x1FC000
+//w_cnt_top:	.word 0x1FC000
-//w_cnt_top:	.word 0x1		//for simulation only
+w_cnt_top:	.word 0x1		//for simulation only
 
 main:
 ldr r0,>addr	//LED addr

programs/can_test.prog_

@@ -0,0 +1,71 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+timer_interrupt:
+    reti
+    nop
+
+can_interrupt:
+    br >can_interrupt
+    nop
+
+.align
+led_addr: .word 0x000F0000
+
+timer_counter_addr: .word 0x000F0008
+timer_status_addr: .word 0x000F000C
+
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+
+priority_mask: .word 0xFFFFFF03
+
+timer_target_value: .word 127 // for simulation
+// timer_target_value: .word 0xF10000 // for real board
+
+can_base_addr: .word 0x000F0100
+
+can_control_ptr: .word =can_base_addr
+can_command_ptr: .word =can_base_addr + 1
+can_acceptance_code_ptr: .word =can_base_addr + 4
+can_acceptance_mask_ptr: .word =can_base_addr + 5
+can_acceptance_bus_timing0_ptr: .word =can_base_addr + 6
+can_acceptance_bus_timing1_ptr: .word =can_base_addr + 7
+can_output_control_ptr: .word =can_base_addr + 8
+can_identifier0_ptr: .word =can_base_addr + 10
+can_identifier1_ptr: .word =can_base_addr + 11
+can_data0_ptr: .word =can_base_addr + 12
+can_data1_ptr: .word =can_base_addr + 13
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    // Set LED to pattern
+    clr r2
+    addi r2, 0x7A
+    st08 r0, r2
+
+    // Initialize CAN
+    ldr r0, >can_acceptance_code_ptr
+
+loop:
+    br >loop
+    nop
+
+can_interrupt:
+    reti
+    nop

programs/interrupt_test.prog

@@ -0,0 +1,54 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+switches_interrupt:
+    br >switches_interrupt_handler
+    nop
+
+can_interrupt:
+    br >can_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    ldr r0, >led_addr
+    ldr r1, >switches_addr
+
+loop:
+    br >loop
+    nop
+
+switches_interrupt_handler:
+    ld32 r2, r1
+
+    // Set LED to pattern
+    st08 r0, r2
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    reti
+    nop

programs/project.prog

@@ -0,0 +1,435 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+switches_interrupt:
+    br >switches_interrupt_handler
+    nop
+
+can_interrupt:
+    br >can_interrupt_handler
+    nop
+
+.align
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+scrolling_addr: .word 0x000F00A0
+scrolling_count_addr: .word 0x000F00A4
+
+priority_mask: .word 0xFFFFFF03
+write_mask: .word 0x1000000
+clear_mask: .word 0x100
+scrolling_cnt_value: .word 0x10FC000 // for real board
+// scrolling_cnt_value: .word 0x500 // for simulation
+
+// CAN
+can_control_addr: .word 0x000F0100
+can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
+can_acceptance_code_addr: .word 0x000F0104
+can_acceptance_mask_addr: .word 0x000F0105
+can_bus_timing0_addr: .word 0x000F0106
+can_bus_timing1_addr: .word 0x000F0107
+can_output_control_addr: .word 0x000F0108
+
+// CAN Constants
+acceptance_code: .word 0x00
+acceptance_mask: .word 0xFF
+btr0: .word 0x45 // for Real board
+btr1: .word 0x16 // for Real board
+// btr0: .word 0x80
+// btr1: .word 0x48
+output_control: .word 0x02
+control: .word 0xFE
+rx_interrupt_mask: .word 0x01
+tx_interrupt_mask: .word 0x02
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    // --- CAN init ---
+    ldr r0, >can_acceptance_code_addr
+    ldr r3, >acceptance_code
+    st08 r0, r3
+
+    ldr r0, >can_acceptance_mask_addr
+    ldr r3, >acceptance_mask
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing0_addr
+    ldr r3, >btr0
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing1_addr
+    ldr r3, >btr1
+    st08 r0, r3
+
+    ldr r0, >can_output_control_addr
+    ldr r3, >output_control
+    st08 r0, r3
+
+    ldr r0, >can_control_addr
+    ldr r3, >control
+    st08 r0, r3
+
+    // Start scrolling controller
+    ldr r0, >scrolling_addr
+    clr r3
+    addi r3, 0x01
+    st32 r0, r3
+
+    // (Re)set scrolling speed
+    ldr r5, >scrolling_count_addr
+    ldr r4, >scrolling_cnt_value
+    st32 r5, r4
+
+    // Set LED to state
+    ldr r0, >led_addr
+    clr r3
+    addi r3, 0x7A
+    st08 r0, r3
+
+loop:
+    br >loop
+    nop
+
+.align
+button_data_add: .word 0x10000
+button_data_clear: .word 0x20000
+button_frequency: .word 0x40000
+
+switches_interrupt_handler:
+    // Read switch state
+    ldr r0, >switches_addr
+    ld32 r2, r0
+
+    ldr r0, >led_addr
+    st08 r0, r2
+
+    clr r4
+
+    ldr r3, >button_data_clear
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_data_clear_frame
+    nop
+
+    ldr r3, >button_data_add
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_data_add_frame
+    nop
+
+    ldr r3, >button_frequency
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_frequency_frame
+    nop
+
+    // Unimplemented button function
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    // Dispatch interrupt event
+    ldr r0, >can_interrupt_addr
+    ld08 r1, r0
+    clr r4
+
+    ldr r2, >rx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_rx_handler
+    nop
+
+    ldr r2, >tx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_tx_handler
+    nop
+
+    // Unimplemented CAN interrupt
+    reti
+    nop
+
+.align
+can_tx_data0_addr: .word 0x000F010C
+can_tx_data1_addr: .word 0x000F010D
+can_tx_data2_addr: .word 0x000F010E
+
+can_tx_identifier0_addr: .word 0x000F010A
+can_tx_identifier1_addr: .word 0x000F010B
+
+id0: .word 0xAA
+id1_0: .word 0xC1 // data length is also encoded here
+id1_1: .word 0xC2 // data length is also encoded here
+id1_2: .word 0xC3 // data length is also encoded here
+
+frame_data_add: .word 0x00
+frame_data_clear: .word 0x01
+frame_frequency: .word 0x02
+
+can_command_addr_ptr: .word =can_command_addr
+
+can_send_data_clear_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_0
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_data_clear
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+.align
+byte_mask: .word 0xFF
+
+can_send_data_add_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_1
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_data_add
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    // r2 is still switches reg
+    ldr r0, >can_tx_data1_addr
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r7
+    add r7, r7, r2
+    ldr r4, >byte_mask
+    and r7, r7, r4
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+.align
+can_rx_data0_addr: .word 0x000F0116
+
+can_rx_handler:
+    // Dispatch CAN frame
+    ldr r0, >can_rx_data0_addr
+    ld08 r6, r0
+
+    ldr r2, >frame_data_clear
+    cmp eq r2, r6
+    br true >can_handle_data_clear_frame
+    nop
+
+    ldr r2, >frame_data_add
+    cmp eq r2, r6
+    br true >can_handle_data_add_frame
+    nop
+
+    ldr r2, >frame_frequency
+    cmp eq r2, r6
+    br true >can_handle_frequency_frame
+    nop
+
+    // Unimplemented CAN frame
+    reti
+    nop
+
+can_tx_handler:
+    // Dispatch CAN frame
+
+    ldr r2, >frame_data_clear
+    cmp eq r2, r6
+    br true >handle_data_clear_frame
+    nop
+
+    ldr r2, >frame_data_add
+    cmp eq r2, r6
+    br true >handle_data_add_frame
+    nop
+
+    ldr r2, >frame_frequency
+    cmp eq r2, r6
+    br true >handle_frequency_frame
+    nop
+
+    reti
+    nop
+
+can_send_frequency_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_2
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_frequency
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    // r2 is still switches reg
+    ldr r0, >can_tx_data1_addr
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r7
+    add r7, r7, r2
+    ldr r4, >byte_mask
+    and r7, r7, r4
+
+    ldr r0, >can_tx_data2_addr
+    rsh r2, r2, 8
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r8
+    add r8, r8, r2
+    ldr r4, >byte_mask
+    and r8, r8, r4
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+can_handle_data_clear_frame:
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_data_clear_frame:
+    ldr r0, >scrolling_addr_ptr
+    ldr r1, >clear_mask_ptr
+
+    ld32 r0, r0
+    ld32 r1, r1
+
+    st32 r0, r1
+
+    reti
+    nop
+
+.align
+scrolling_addr_ptr: .word =scrolling_addr
+write_mask_ptr: .word =write_mask
+can_command_addr_ptr0: .word =can_command_addr
+can_rx_data1_addr: .word 0x000F0117
+can_rx_data2_addr: .word 0x000F0118
+
+can_handle_data_add_frame:
+    ldr r0, >can_rx_data1_addr
+    ld08 r7, r0
+
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr0
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_data_add_frame:
+    // Expect symbol to add in r7 register
+
+    ldr r0, >scrolling_addr_ptr
+    ld32 r0, r0
+
+    ldr r1, >write_mask_ptr
+    ld32 r1, r1
+
+    lsh r7, r7, 16
+    or r4, r7, r1
+    st32 r0, r4
+
+    reti
+    nop
+
+.align
+clear_mask_ptr: .word =clear_mask
+scrolling_count_addr_ptr: .word =scrolling_count_addr
+
+can_handle_frequency_frame:
+    ldr r0, >can_rx_data1_addr
+    ld08 r7, r0
+
+    ldr r0, >can_rx_data2_addr
+    ld08 r8, r0
+
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr0
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_frequency_frame:
+    // Expect count value in r7 and r8 register
+
+    // For real board shift the count value by 16!
+
+    // Concat bits
+    lsh r8, r8, 8
+    or r8, r8, r7
+    lsh r8, r8, 16 // real board !!!
+
+    ldr r0, >scrolling_count_addr_ptr
+    ld32 r0, r0
+
+    st32 r0, r8
+
+    reti
+    nop

programs/project_init.prog

@@ -0,0 +1,117 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+switches_interrupt:
+    br >switches_interrupt_handler
+    nop
+
+can_interrupt:
+    br >can_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+
+// CAN
+can_control_addr: .word 0x000F0100
+can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
+can_acceptance_code_addr: .word 0x000F0104
+can_acceptance_mask_addr: .word 0x000F0105
+can_bus_timing0_addr: .word 0x000F0106
+can_bus_timing1_addr: .word 0x000F0107
+can_output_control_addr: .word 0x000F0108
+can_identifier0_addr: .word 0x000F010A
+can_identifier1_addr: .word 0x000F010B
+can_data0_addr: .word 0x000F010C
+can_data1_addr: .word 0x000F010D
+
+// CAN Constants
+acceptance_code: .word 0x00
+acceptance_mask: .word 0xFF
+// btr0: .word 0x45 Real board
+// btr1: .word 0x16 Real board
+btr0: .word 0x80
+btr1: .word 0x48
+output_control: .word 0x02
+control: .word 0xFE
+id0: .word 0xAA
+id1: .word 0xC2
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    // --- CAN init ---
+    ldr r0, >can_acceptance_code_addr
+    ldr r3, >acceptance_code
+    st08 r0, r3
+
+    ldr r0, >can_acceptance_mask_addr
+    ldr r3, >acceptance_mask
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing0_addr
+    ldr r3, >btr0
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing1_addr
+    ldr r3, >btr1
+    st08 r0, r3
+
+    ldr r0, >can_output_control_addr
+    ldr r3, >output_control
+    st08 r0, r3
+
+    ldr r0, >can_control_addr
+    ldr r3, >control
+    st08 r0, r3
+
+    ldr r0, >led_addr
+    ldr r1, >switches_addr
+
+    st08 r0, r2
+loop:
+    br >loop
+    nop
+
+switches_interrupt_handler:
+    ld32 r2, r1
+
+    // Set LED to pattern
+    st08 r0, r2
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    reti
+    nop
+
+wait:
+	clr r7
+    clr r8
+    addi r8, 16
+inc_i:
+	cmp neq r7,r8
+	br true >inc_i
+	addi r7,1
+	ret
+    nop

programs/scrolling.prog

@@ -0,0 +1,260 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+scrolling_addr: .word 0x000F00A0
+scrolling_count_addr: .word 0x000F00A4
+
+// scrolling_cnt_value: .word 0x20FC000 // for real board
+scrolling_cnt_value: .word 0x500 // for simulation
+
+// w_cnt_top:  .word 0x3FC000 // for real board
+w_cnt_top:    .word 0x100 //for simulation
+
+pattern_ptr: .word =pattern1
+
+pattern1:
+    .word 0x01030204
+    .word 0x05070608
+    .word 0x090B0A0C
+    .word 0x0D0F0E00
+
+pattern2:
+    .word 0x0F0E0E0B
+    .word 0x100D0A0E
+    .word 0x0D101010
+
+pattern3:
+    .word 0x01101010
+
+pattern4:
+    .word 0x02031010
+
+pattern5:
+    .word 0x00000000
+    .word 0x00101010
+
+write_mask:
+    .word 0x1000000
+
+clear_mask:
+    .word 0x100
+
+display_char:
+    // Read from ptr r3
+    ld08 r4, r3
+    lsh r4, r4, 16
+    or r4, r4, r1
+    st32 r0, r4
+    ret
+    nop
+
+main:
+    ldr r8, >w_cnt_top
+
+    ldr r0, >scrolling_addr
+    ldr r1, >write_mask
+    ldr r2, >clear_mask
+    ldr r10, >pattern_ptr
+
+number_loop:
+    // (Re)set scrolling speed
+    ldr r5, >scrolling_count_addr
+    ldr r7, >scrolling_cnt_value
+    st32 r5, r7
+
+    // --------- 132457689BACDFE0 ---------
+    clr r3
+    add r3, r3, r10
+    call >display_char
+    nop
+
+    clr r7 
+    clr r11
+    addi r11, 15 // iterations
+display_loop0:
+    addi r3, 0x01
+    call >display_char
+    nop
+
+    addi r7, 1
+    cmp neq r7, r11
+    br true >display_loop0
+    nop
+
+    // Turn on
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // Turn off
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    // Double scrolling speed
+    ldr r5, >scrolling_count_addr
+    ldr r7, >scrolling_cnt_value
+    rsh r7, r7, 1 // Divide by 2
+    st32 r5, r7
+
+    // Clear
+    clr r4
+    or r4, r4, r2
+    st32 r0, r4
+
+    // --------- DEAD BEEF ---------
+    clr r7 
+    clr r11
+    addi r11, 12 // iterations
+display_loop1:
+    addi r3, 0x01
+    call >display_char
+    nop
+
+    addi r7, 1
+    cmp neq r7, r11
+    br true >display_loop1
+    nop
+
+    // Turn on
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // Turn off
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    // Clear
+    clr r4
+    or r4, r4, r2
+    st32 r0, r4
+
+    // --------- 1 ---------
+    clr r7 
+    clr r11
+    addi r11, 4 // iterations
+display_loop2:
+    addi r3, 0x01
+    call >display_char
+    nop
+
+    addi r7, 1
+    cmp neq r7, r11
+    br true >display_loop2
+    nop
+
+    // Turn on
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // Turn off
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    // Clear
+    clr r4
+    or r4, r4, r2
+    st32 r0, r4
+
+    // --------- 2 3 ---------
+    clr r7 
+    clr r11
+    addi r11, 4 // iterations
+display_loop3:
+    addi r3, 0x01
+    call >display_char
+    nop
+
+    addi r7, 1
+    cmp neq r7, r11
+    br true >display_loop3
+    nop
+
+    // Turn on
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // Turn off
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    // Clear
+    clr r4
+    or r4, r4, r2
+    st32 r0, r4
+
+    // --------- 0 0 0 0 0 ---------
+    clr r7 
+    clr r11
+    addi r11, 8
+    
+     // iterations
+display_loop4:
+    addi r3, 0x01
+    call >display_char
+    nop
+
+    addi r7, 1
+    cmp neq r7, r11
+    br true >display_loop4
+    nop
+
+    // Turn on
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // Turn off
+    clr r4
+    addi r4, 0x1
+    st32 r0, r4
+
+    br always >number_loop
+    nop
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+    clr r6                // outer counter
+    clr r9
+    addi r9, 0x7F
+    inc_o:
+    clr r7
+    inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    cmp neq r6,r9         // else, if i=cnt_outer
+    br true >inc_o
+    addi r6,1             // else
+    ret                    
+    nop

programs/segments_adv_test.prog

@@ -0,0 +1,170 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+segment_addr: .word 0x000F00A0
+
+w_cnt_top:  .word 0xFFC000
+// w_cnt_top:    .word 0x100 //for simulation only
+
+write_and_shift:
+    .word 0x01000100
+
+main:
+    ldr r8, >w_cnt_top
+    ldr r0, >segment_addr
+    ldr r1, >write_and_shift
+
+number_loop:
+    // 0 1 2 3 4 5 6 7
+    clr r4
+    addi r4, 0x0
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x1
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x2
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x3
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x4
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x5
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x6
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x7
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 8 9 A B C D E F
+    clr r4
+    addi r4, 0x8
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x9
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xA
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xB
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xC
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xF
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 0xDEADBEEF pattern:
+    clr r4
+    addi r4, 0xF
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xB
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xA
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    br always >number_loop
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+    inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

programs/segments_test.prog

@@ -0,0 +1,98 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+led_addr: .word 0x000F0000
+
+number_array0:
+    .word 0x03020100
+number_array1:
+    .word 0x07060504
+number_array2:
+    .word 0x0B0A0908
+number_array3:
+    .word 0x0F0E0D0C
+
+segment_addr0: .word 0x000F00A0
+segment_addr1: .word 0x000F00A4
+
+random_value: .word 0xAA
+
+w_cnt_top:  .word 0xFFFFFF // for real board
+// w_cnt_top:    .word 0x100 //for simulation only
+
+infamous_pattern0:
+    .word 0x0F0E0E0B
+infamous_pattern1:
+    .word 0x0D0A0E0D
+
+main:
+    ldr r8, >w_cnt_top
+    ldr r0, >led_addr
+
+    // Set LEDs to some value
+    ldr r4, >random_value
+    st08 r0, r4
+
+number_loop:
+    // First 4
+    ldr r4, >number_array0
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >number_array1
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // First 4
+    ldr r4, >number_array2
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >number_array3
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 0xDEADBEEF pattern:
+
+    // First 4
+    ldr r4, >infamous_pattern0
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >infamous_pattern1
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    br always >number_loop
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+    inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

programs/timer_blinky.prog

@@ -0,0 +1,102 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+timer_interrupt:
+    br >timer_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+timer_counter_addr: .word 0x000F0008
+timer_status_addr: .word 0x000F000C
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+timer_target_value: .word 127 // for simulation
+// timer_target_value: .word 0xF10000 // for real board
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    ldr r0,>led_addr                // LED addr
+    ldr r1,>timer_status_addr      // Timer addr
+    ldr r3,>timer_counter_addr      // Timer addr
+
+    // Init
+    clr r9 // 0 if we are currently filling, 1 if we are currently flushing
+    clr r8 // shift register
+    clr r5 // shift counter
+    clr r4 // shift counter top constant
+    addi r4, 10
+
+    // Enable the timer...
+    ldr r2, >timer_target_value // target value
+    st32 r3, r2
+
+    clr r2
+    addi r2, 0x3 // enable and repeat bit set
+    st32 r1, r2
+
+loop:
+    br >loop
+    nop
+
+timer_interrupt_handler:
+     clr r10
+     addi r10, 1
+     cmp eq r9, r10
+     br true >flush
+     nop
+     br always >fill
+     nop
+
+rst_fill:
+     clr r5
+fill:
+     clr r9
+
+     // When shift register full, jump to flush
+     addi r5, 1
+     cmp eq r5, r4
+     br true >rst_flush
+     nop
+
+     lsh r8, r8, 1
+     addi r8, 1
+     st08 r0, r8
+
+     reti
+     nop
+
+rst_flush:
+     clr r5
+flush:
+     clr r9
+     addi r9, 1
+
+     // When shift register empty, jump to fill
+     addi r5, 1
+     cmp eq r5, r4
+     br true >rst_fill
+     nop
+
+     lsh r8, r8, 1
+     st08 r0, r8
+
+     reti
+     nop
+

programs/timer_test.prog

@@ -0,0 +1,56 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+timer_interrupt:
+    br >timer_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+timer_counter_addr: .word 0x000F0008
+timer_status_addr: .word 0x000F000C
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    ldr r0,>led_addr                // LED addr
+    ldr r1,>timer_status_addr      // Timer addr
+
+    // Set some LEDs
+    clr r2
+    addi r2, 0x5A
+    st08 r0, r2
+
+    // Enable the timer...
+    clr r2
+    addi r2, 0x1 // enable bit set
+    st08 r1, r2
+
+loop:
+    br >loop
+    nop
+
+
+timer_interrupt_handler:
+    // Set LEDs to indicate we reached the timer interrupt
+    clr r2
+    addi r2, -1
+    st08 r0, r2
+    reti

soc/core/irq_controller.vhd

@@ -97,7 +97,7 @@ begin
 		variable num_highest  : unsigned(irq_num_width - 1 downto 0)  := (others => '0');
 	begin
 		-- if not in request, and something is pending (ignoring startup uninitialized state)
-		if ((rst = '0') and ((pending /= (pending'range => '0')) and (pending /= (pending'range => 'U')))) then
+		if ((rst = '0') and ((pending /= (pending'range => '0')))) then --and (pending /= (pending'range => 'U')))) then
 			-- something is pending
 
 			-- initialize variables before loop

soc/core/lt16x32_global.vhd

@@ -8,7 +8,7 @@ package lt16x32_global is
 	-- width of the memory, the core supports 32 only
 	constant memory_width   : integer := 32;
 	-- width of the vector holding the interrupt number, maximum 7 due to processor architecture
-	constant irq_num_width  : integer := 4;
+	constant irq_num_width  : integer := 5;
 	-- width of the vector holding the interrupt priority, maximum 6 due to processor architecture
 	constant irq_prio_width : integer := 4;
 

soc/lib/config.vhd

@@ -27,6 +27,10 @@ package config is
 	constant CFG_MEM : integer := 0;
 	constant CFG_DMEM : integer := CFG_MEM+1;
 	constant CFG_LED : integer := CFG_DMEM+1;
+	constant CFG_SW : integer := CFG_LED+1;
+	constant CFG_TIMER : integer := CFG_SW+1;
+    constant CFG_SCR : integer := CFG_TIMER+1;
+    constant CFG_CAN : integer := CFG_SCR+1;
 
 -----------------------------
 -- base address (BADR) & mask address (MADR)
@@ -36,12 +40,21 @@ package config is
 	constant CFG_BADR_DMEM		: generic_addr_type := CFG_BADR_MEM + IMEMSZ*4; --16#00000400#;
 	--constant CFG_BADR_NEXTFREEADDRESS		: generic_addr_type := 16#00000800#;
 	constant CFG_BADR_LED		: generic_addr_type := 16#000F0000#;
+	constant CFG_BADR_SW		: generic_addr_type := 16#000F0004#;
+	constant CFG_BADR_TIMER		: generic_addr_type := 16#000F0008#;
+    constant CFG_BADR_SCR		: generic_addr_type := 16#000F00A0#;
+    constant CFG_BADR_CAN       : generic_addr_type := 16#000F0100#;
+
 -- mask addr
 	constant CFG_MADR_ZERO		: generic_mask_type := 0;
 	constant CFG_MADR_FULL		: generic_mask_type := 16#3FFFFF#;
 	constant CFG_MADR_MEM		: generic_mask_type := 16#3FFFFF# - (IMEMSZ*4 -1);
 	constant CFG_MADR_DMEM		: generic_mask_type := 16#3FFFFF# - (256 -1); -- uses 6 word-bits, size 256 byte
 	constant CFG_MADR_LED		: generic_mask_type := 16#3FFFFF#; -- size=1 byte
+	constant CFG_MADR_SW		: generic_mask_type := 16#3FFFFF# - (4 - 1); -- size=4 byte
+	constant CFG_MADR_TIMER		: generic_mask_type := 16#3FFFFF# - (8 - 1); -- size=8 byte (2 words)
+    constant CFG_MADR_SCR		: generic_mask_type := 16#3FFFFF# - (8 - 1); -- size=8 byte
+    constant CFG_MADR_CAN		: generic_mask_type := 16#3FFFFF# - (256 - 1); -- size=256 byte
 
 end package config;
 

soc/peripheral/hex2physical.vhd

@@ -0,0 +1,42 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lt16x32_global.all;
+use work.config.all;
+
+entity hex2physical is
+	port(
+		hex : in std_logic_vector(4 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+	);
+end hex2physical;
+
+architecture Behavioral of hex2physical is
+begin
+
+    process(hex)
+    begin
+        case hex is
+            when "10000" => cathodes <= not "11111100"; -- "0"
+            when "10001" => cathodes <= not "01100000"; -- "1"
+            when "10010" => cathodes <= not "11011010"; -- "2"
+            when "10011" => cathodes <= not "11110010"; -- "3" 
+            when "10100" => cathodes <= not "01100110"; -- "4"
+            when "10101" => cathodes <= not "10110110"; -- "5" 
+            when "10110" => cathodes <= not "10111110"; -- "6" 
+            when "10111" => cathodes <= not "11100000"; -- "7" 
+            when "11000" => cathodes <= not "11111110"; -- "8"     
+            when "11001" => cathodes <= not "11110110"; -- "9"
+            when "11010" => cathodes <= not "11101110"; -- "A"
+            when "11011" => cathodes <= not "00111110"; -- "B"
+            when "11100" => cathodes <= not "10011100"; -- "C"
+            when "11101" => cathodes <= not "01111010"; -- "D"
+            when "11110" => cathodes <= not "10011110"; -- "E"
+            when "11111" => cathodes <= not "10001110"; -- "F"
+            when others => cathodes <= not "00000000"; -- "Off"
+        end case;
+    end process;
+
+end Behavioral;

soc/peripheral/peripherals.vhd

@@ -12,6 +12,22 @@ use work.config.all;
 
 package lt16soc_peripherals is
 
+    component can_vhdl_top is
+        generic(
+            memaddr	 : generic_addr_type;
+            addrmask : generic_mask_type
+        );
+        port(
+            clk	 : in std_logic;
+            rstn	 : in std_logic;
+            wbs_i	 : in wb_slv_in_type;
+            wbs_o	 : out wb_slv_out_type;
+            rx_i	 : in std_logic;
+            tx_o	 : out std_logic;
+            irq_on	 : out std_logic
+        );
+    end component can_vhdl_top;
+
 	component wb_led is
 	generic(
 		memaddr		:	generic_addr_type;-- := CFG_BADR_LED;
@@ -26,6 +42,55 @@ package lt16soc_peripherals is
 	);
 	end component;
 
+	component wb_switches is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_SW;
+		addrmask	:	generic_mask_type --:= CFG_MADR_SW;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        buttons : in std_logic_vector(4 downto 0);
+        switches : in std_logic_vector(15 downto 0);
+
+        interrupt : out std_logic
+	);
+	end component;
+
+	component wb_timer is
+		generic(
+			memaddr		:	generic_addr_type; --:= CFG_BADR_TIMER;
+			addrmask	:	generic_mask_type --:= CFG_MADR_TIMER;
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in  std_logic;
+			wslvi	:	in	wb_slv_in_type;
+			wslvo	:	out	wb_slv_out_type;
+
+			interrupt : out std_logic
+		);
+	end component;
+
+    component wb_scrolling is
+        generic(
+            memaddr		:	generic_addr_type; --:= CFG_BADR_SCR;
+            addrmask	:	generic_mask_type --:= CFG_MADR_SCR;
+        );
+        port(
+            clk		: in  std_logic;
+            rst		: in  std_logic;
+            wslvi	:	in	wb_slv_in_type;
+            wslvo	:	out	wb_slv_out_type;
+    
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+        );
+    end component;
+
 end lt16soc_peripherals;
 
 package body lt16soc_peripherals is

soc/peripheral/scrolling_buffer.vhd

@@ -0,0 +1,89 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scrolling_buffer is
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        buffer_clear : in std_logic;
+        buffer_write : in std_logic;
+        buffer_data : in std_logic_vector(4 downto 0);
+        next_char : in std_logic;
+        hex_char : out std_logic_vector(4 downto 0);
+        elements : out std_logic_vector(4 downto 0)
+    );
+end entity scrolling_buffer;
+
+architecture Behavioral of scrolling_buffer is
+
+    constant BUFFER_SIZE : integer := 16; 
+
+    type ring_buffer_type is array (0 to BUFFER_SIZE - 1) of std_logic_vector(4 downto 0);
+    signal ptr_write : integer range 0 to BUFFER_SIZE - 1;
+    signal ptr_read : integer range 0 to BUFFER_SIZE - 1;
+    signal ptr_last : integer range -1 to BUFFER_SIZE - 1;
+    
+    signal ring_buffer : ring_buffer_type;
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+                ptr_last <= -1;
+                ptr_write <= 0;
+                ring_buffer <= (others => (others => '0'));
+                elements <= (others => '0');
+            else
+                if buffer_write = '1' then
+                    ring_buffer(ptr_write) <= buffer_data;
+                    
+                    if ptr_last /= BUFFER_SIZE - 1 then
+                        ptr_last <= ptr_write;
+                        elements <= std_logic_vector(to_unsigned(ptr_write + 1, 5));
+                    end if;
+
+                    if ptr_write = BUFFER_SIZE - 1 then
+                        ptr_write <= 0;
+                    else
+                        ptr_write <= ptr_write + 1;
+                    end if;
+                elsif buffer_clear = '1' then
+                    ptr_last <= -1;
+                    ptr_write <= 0;
+                    elements <= (others => '0');
+                    ring_buffer <= (others => (others => '0'));
+                end if;
+            end if;
+		end if;
+	end process;
+
+    process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+                ptr_read <= 0;
+                hex_char <= (others => '1');
+            else
+                if ptr_last = -1 then -- Special case
+                    hex_char <= (others => '1');
+                else
+                    hex_char <= ring_buffer(ptr_read);
+                end if;
+                
+                if buffer_clear = '1' then
+                    ptr_read <= 0;
+                elsif next_char = '1' then    
+                    if ptr_read = ptr_last then
+                        ptr_read <= 0;
+                    else
+                        ptr_read <= ptr_read + 1;
+                    end if;
+                end if;
+            end if;
+		end if;
+	end process;
+
+end Behavioral;

soc/peripheral/scrolling_controller.vhd

@@ -0,0 +1,137 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scrolling_controller is
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        on_off : in std_logic;
+        cnt_start : out std_logic;
+        cnt_done : in std_logic;
+        next_char : out std_logic;
+        hex_char : in std_logic_vector(4 downto 0);
+        seg_data : out std_logic_vector(3 downto 0);
+        seg_off : out std_logic;
+        seg_shift : out std_logic;
+        seg_write : out std_logic;
+        seg_clear : out std_logic;
+        buffer_elements : in std_logic_vector(4 downto 0)
+    );
+end entity scrolling_controller;
+
+architecture Behavioral of scrolling_controller is
+
+    type state_type is (s_off, s_wait, s_update);
+    signal state : state_type;
+    
+    signal current_element : integer range 0 to 16;
+    signal current_resetted : std_logic;
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+                state <= s_off;
+                cnt_start <= '0';
+                next_char <= '0';
+
+                seg_shift <= '0';
+                seg_write <= '0';
+                seg_clear <= '0';
+
+                current_element <= 0;
+            else
+                case state is
+                    when s_off =>
+                        current_element <= 0;
+                        
+                        if on_off = '0' then
+                            state <= s_off;
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
+                            cnt_start <= '0';
+                            next_char <= '0';
+                        else
+                            state <= s_update;
+                            -- seg_shift <= '1';
+                            -- seg_write <= '1';
+                            -- seg_off <= hex_char(4);
+                            -- seg_data <= hex_char(3 downto 0);
+                            -- seg_clear <= '0';
+                            cnt_start <= '1';
+                            next_char <= '0';
+                            current_element <= current_element + 1;
+                        end if;
+                    when s_wait =>
+                        if on_off = '1' then
+                            state <= s_off;
+                            seg_clear <= '1';
+                            seg_write <= '0';
+                            seg_shift <= '0';
+                            cnt_start <= '0';
+                            next_char <= '0';
+                        elsif cnt_done = '0' then
+                            state <= s_wait;
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
+                            cnt_start <= '0';
+                            next_char <= '0';
+                        else -- cnt_done = '1'
+                            state <= s_update;
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
+                            cnt_start <= '1';
+
+                            -- if current_element < unsigned(buffer_elements) then
+                            --     next_char <= '1';
+                            -- else
+                                -- next_char <= '0';
+                            -- end if;
+
+                            if current_element = 15 then
+                                current_element <= 1;
+                            else
+                                current_element <= current_element + 1;
+                            end if;
+                        end if;
+                    when s_update =>
+                        if on_off = '0' then
+                            state <= s_wait;
+                            seg_shift <= '1';
+                            seg_write <= '1';
+                            seg_clear <= '0';
+                            cnt_start <= '0';
+                            
+                            if current_element <= unsigned(buffer_elements) then
+                                next_char <= '1';
+                            else
+                                next_char <= '0';
+                            end if;
+
+                            if current_element <= unsigned(buffer_elements) then
+                                seg_data <= hex_char(3 downto 0);
+                                seg_off <= hex_char(4);
+                            else
+                                seg_data <= x"0";
+                                seg_off <= '1';
+                            end if;
+                        else
+                            state <= s_off;
+                            seg_clear <= '1';
+                            seg_write <= '0';
+                            seg_shift <= '0';
+                            cnt_start <= '0';
+                            next_char <= '0';
+                        end if;
+                end case;
+            end if;
+		end if;
+	end process;
+
+end Behavioral;

soc/peripheral/scrolling_timer.vhd

@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scrolling_timer is
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        cnt_start : in std_logic;
+        cnt_done : out std_logic;
+        cnt_value : in std_logic_vector(31 downto 0)
+    );
+end entity scrolling_timer;
+
+architecture Behavioral of scrolling_timer is
+
+	signal counter : std_logic_vector(31 downto 0);
+    signal done : std_logic;
+    signal counting : std_logic;
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				counter <= x"00000000";
+				done <= '0';
+				counting <= '0';
+			else
+                counter <= x"00000000";
+                done <= '0';
+
+				if counter >= cnt_value and counting = '1' then
+                    counter <= x"00000000";
+                    done <= '1';
+                    counting <= '0';
+                elsif counting = '1' then
+                    counter <= std_logic_vector(unsigned(counter) + 1);
+                elsif counting = '0' and cnt_start = '1' then
+                    counting <= '1';
+                end if;
+			end if;
+		end if;
+	end process;
+
+    cnt_done <= done;
+
+end Behavioral;

soc/peripheral/scrolling_top.vhd

@@ -0,0 +1,247 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+
+entity wb_scrolling is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_SCR;
+		addrmask	:	generic_mask_type --:= CFG_MADR_SCR;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        anodes : out std_logic_vector(7 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+	);
+end wb_scrolling;
+
+architecture Behavioral of wb_scrolling is
+
+    signal cnt_start : std_logic;
+    signal cnt_done : std_logic;
+    signal cnt_value : std_logic_vector(31 downto 0);
+
+    signal buffer_clear : std_logic;
+    signal buffer_write : std_logic;
+    signal buffer_data : std_logic_vector(4 downto 0);
+    signal buffer_elements : std_logic_vector(4 downto 0);
+
+    signal seg_data : std_logic_vector(3 downto 0);
+    signal seg_off : std_logic;
+    signal seg_shift : std_logic;
+    signal seg_write : std_logic;
+    signal seg_clear : std_logic;   
+
+    signal on_off : std_logic;
+
+    signal next_char : std_logic;
+    signal hex_char : std_logic_vector(4 downto 0);
+
+    signal data_out : std_logic_vector(63 downto 0);
+    signal data_in : std_logic_vector(63 downto 0);
+    signal data_in_changed : std_logic;
+    
+    signal ack : std_logic;
+
+    component scrolling_timer is
+        port(
+            clk : in std_logic;
+            rst : in std_logic;
+            cnt_start : in std_logic;
+            cnt_done : out std_logic;
+            cnt_value : in std_logic_vector(31 downto 0)
+        );
+    end component;
+
+    component scrolling_buffer
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        buffer_clear : in std_logic;
+        buffer_write : in std_logic;
+        buffer_data : in std_logic_vector(4 downto 0);
+        next_char : in std_logic;
+        hex_char : out std_logic_vector(4 downto 0);
+        elements : out std_logic_vector(4 downto 0)
+    );
+    end component;
+
+    component scrolling_controller
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        on_off : in std_logic;
+        cnt_start : out std_logic;
+        cnt_done : in std_logic;
+        next_char : out std_logic;
+        hex_char : in std_logic_vector(4 downto 0);
+        seg_data : out std_logic_vector(3 downto 0);
+        seg_off : out std_logic;
+        seg_shift : out std_logic;
+        seg_write : out std_logic;
+        seg_clear : out std_logic;
+        buffer_elements : in std_logic_vector(4 downto 0)
+    );
+    end component;
+
+    component seven_segment_display is
+		port(
+            clk		: in  std_logic;
+            rst		: in  std_logic;
+            seg_data : in std_logic_vector(3 downto 0);
+            seg_off : in std_logic;
+            seg_shift : in std_logic;
+            seg_write : in std_logic;
+            seg_clear : in std_logic;   
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+		);
+	end component;
+
+begin
+
+	timer: scrolling_timer
+        port map(
+			clk => clk,
+            rst => rst,
+            cnt_start => cnt_start,
+            cnt_done => cnt_done,
+            cnt_value => cnt_value
+    );
+
+    buf: scrolling_buffer
+    port map(
+        clk => clk,
+        rst => rst,
+        buffer_clear => buffer_clear,
+        buffer_write => buffer_write,
+        buffer_data => buffer_data,
+        next_char => next_char,
+        hex_char => hex_char,
+        elements => buffer_elements
+    );
+
+    controller: scrolling_controller
+    port map(
+        clk => clk,
+        rst => rst,
+        on_off => on_off,
+        cnt_start => cnt_start,
+        cnt_done => cnt_done,
+        next_char => next_char,
+        hex_char => hex_char,
+        seg_data => seg_data,
+        seg_off => seg_off,
+        seg_shift => seg_shift,
+        seg_write => seg_write,
+        seg_clear => seg_clear,
+        buffer_elements => buffer_elements
+    );
+
+    seven_segment: seven_segment_display
+    port map(
+        clk => clk,
+        rst	=> rst,
+        seg_data => seg_data,
+        seg_off => seg_off,
+        seg_shift => seg_shift,
+        seg_write => seg_write,
+        seg_clear => seg_clear,
+
+        anodes => anodes,
+        cathodes => cathodes
+    );
+
+    process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				ack	<= '0';
+                data_in <= (others => '0');
+                data_in_changed <= '0';
+			else
+                data_in <= (others => '0');
+                data_in_changed <= '0';
+                
+				if wslvi.stb = '1' and wslvi.cyc = '1' then
+				    if wslvi.we='0' then
+                        -- data_out will have the correct value
+                    else
+                        -- Write enable
+                        data_in_changed <= '1';
+                        
+                        if wslvi.adr(2) = '0' then 
+                            data_in(31 downto 0) <= dec_wb_dat(wslvi.sel,wslvi.dat);
+                        else
+                            data_in(63 downto 32) <= dec_wb_dat(wslvi.sel,wslvi.dat);
+                        end if;
+                    end if;
+				
+					if ack = '0' then
+						ack	<= '1';
+					else
+						ack	<= '0';
+					end if;
+				else
+					ack <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+    process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				cnt_value <= (others => '0');
+                buffer_write <= '0';
+                buffer_clear <= '0';
+                buffer_data <= (others => '0');
+                on_off <= '0';
+			else
+			    buffer_write <= '0';
+                buffer_clear <= '0';
+                buffer_data <= (others => '0');
+                on_off <= '0';
+                
+                if data_in_changed = '1' and ack = '1' then
+                    if wslvi.adr(2) = '1' then
+                        cnt_value <= data_in(63 downto 32);
+                    else
+                        buffer_write <= data_in(24);
+                        buffer_clear <= data_in(8);
+                        buffer_data <= data_in(20 downto 16);
+                        on_off <= data_in(0);
+                    end if;
+                end if;
+			end if;
+		end if;
+	end process;
+    
+    data_out(31 downto 25) <= (others => '0');
+    data_out(24) <= buffer_write;
+    data_out(23 downto 21) <= (others => '0');
+    data_out(20 downto 16) <= buffer_data;
+    data_out(15 downto 9) <= (others => '0');
+    data_out(8) <= buffer_clear;
+    data_out(7 downto 1) <= (others => '0');
+    data_out(0) <= on_off;
+
+    data_out(63 downto 32) <= cnt_value;
+
+	wslvo.dat <=
+        data_out(31 downto 0) when wslvi.adr(2) = '0' else
+        data_out(63 downto 32) when wslvi.adr(2) = '1';
+
+	wslvo.ack	<= ack;
+	wslvo.wbcfg	<= wb_membar(memaddr, addrmask);
+
+end Behavioral;

soc/peripheral/seven_segment_display.vhd

@@ -0,0 +1,117 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lt16x32_global.all;
+
+entity seven_segment_display is
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+        seg_data : in std_logic_vector(3 downto 0);
+        seg_off : in std_logic;
+        seg_shift : in std_logic;
+        seg_write : in std_logic;
+        seg_clear : in std_logic;   
+        anodes : out std_logic_vector(7 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+	);
+end seven_segment_display;
+
+architecture Behavioral of seven_segment_display is
+
+	signal hex_register : std_logic_vector(63 downto 0);
+    signal hex : std_logic_vector(4 downto 0);
+
+    signal timer_overflow : std_logic;
+    signal overflow_counter : integer range 0 to 7;
+
+    component hex2physical
+    port(
+        hex : in std_logic_vector(4 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+    );
+    end component;
+
+    component simple_timer
+    generic(
+        timer_start : std_logic_vector (31 downto 0)
+    );
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        timer_overflow : out std_logic
+    );
+    end component;
+
+begin
+
+    converter : hex2physical
+    port map(
+        hex => hex,
+        cathodes => cathodes
+    );
+
+    timer: simple_timer
+    generic map (timer_start => x"00000008") -- for simulation
+    -- generic map (timer_start => x"00000F00") -- for board
+    port map(
+        clk => clk,
+        rst => rst,
+        timer_overflow => timer_overflow
+    );
+
+    process(clk)
+    begin
+        if clk'event and clk='1' then
+			if rst = '1' then
+				hex_register <= (others=>'0');
+			else                
+                -- No special care has to be taken to support
+                -- writing and shifting at the same time.
+                
+                if seg_shift = '1' then
+                    hex_register(63 downto 56) <= (others => '0');
+                    hex_register(55 downto 0) <= hex_register(63 downto 8);
+                end if;
+                    
+                if seg_write = '1' then
+                    hex_register(59 downto 56) <= seg_data;
+                    hex_register(60) <= not seg_off; -- unclear if this should only be set when write is 1
+                end if;
+
+                if seg_clear = '1' then
+                    hex_register <= (others => '0');    
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process(clk)
+    begin
+        if clk'event and clk='1' then
+            if rst = '1' then
+                hex <= hex_register(4 downto 0);
+                anodes <= (others => not '0');
+                overflow_counter <= 0;
+            else
+                if seg_clear = '1' then
+                    overflow_counter <= 0;
+                elsif timer_overflow = '1' then
+                    if overflow_counter = 7 then
+                        overflow_counter <= 0;
+                    else
+                        overflow_counter <= overflow_counter + 1;
+                    end if;
+
+                    anodes <= (others => not '0');
+                    anodes(overflow_counter) <= not '1';
+                    
+                    hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
+                end if;
+            end if;
+        end if;
+    end process;
+
+end Behavioral;

soc/peripheral/seven_segment_display_adv.vhd

@@ -0,0 +1,177 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+
+entity wb_segment_adv is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_SEG;
+		addrmask	:	generic_mask_type --:= CFG_MADR_SEG;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        anodes : out std_logic_vector(7 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+	);
+end wb_segment_adv;
+
+architecture Behavioral of wb_segment_adv is
+
+    signal ack : std_logic;
+
+	signal hex_register : std_logic_vector(63 downto 0);
+    signal data_out : std_logic_vector(31 downto 0);
+    signal data_in : std_logic_vector(31 downto 0);
+    signal data_in_changed : std_logic;
+
+    signal hex : std_logic_vector(4 downto 0);
+
+    signal timer_overflow : std_logic;
+    signal overflow_counter : integer range 0 to 7;
+
+    component hex2physical
+    port(
+        hex : in std_logic_vector(4 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+    );
+    end component;
+
+    component simple_timer
+    generic(
+        timer_start : std_logic_vector (31 downto 0)
+    );
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        timer_overflow : out std_logic
+    );
+    end component;
+
+begin
+
+    converter : hex2physical
+    port map(
+        hex => hex,
+        cathodes => cathodes
+    );
+
+    timer: simple_timer
+    generic map (timer_start => x"00000008") -- for simulation
+    -- generic map (timer_start => x"00000F00") -- for board
+    port map(
+        clk => clk,
+        rst => rst,
+        timer_overflow => timer_overflow
+    );
+    
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				ack	<= '0';
+				data_out <= (others=>'0');
+                data_in	<= (others=>'0');
+                data_in_changed <= '0';
+			else
+                data_out <= (others=>'0');
+                data_in	<= (others=>'0');
+                data_in_changed <= '0';
+
+				if wslvi.stb = '1' and wslvi.cyc = '1' then
+				    if wslvi.we='0' then
+                        -- data_out will stay 0
+                    else
+                        -- Write enable
+                        data_in <= dec_wb_dat(wslvi.sel,wslvi.dat);
+                        data_in_changed <= '1';
+                    end if;
+				
+					if ack = '0' then
+						ack	<= '1';
+					else
+						ack	<= '0';
+					end if;
+				else
+					ack <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+    process(clk)
+        variable v_data : std_logic_vector(3 downto 0);
+        variable v_off : std_logic;
+        variable v_write : std_logic;
+        variable v_clear : std_logic;
+        variable v_shift : std_logic;
+    begin
+        if clk'event and clk='1' then
+			if rst = '1' then
+				hex_register <= (others=>'0');
+			else
+                if data_in_changed = '1' and ack = '1' then -- only check if ack was just raised
+                    v_data := data_in(3 downto 0);
+                    v_off := data_in(4);
+                    v_write := data_in(8);
+                    v_clear := data_in(16);
+                    v_shift := data_in(24);
+                    
+                    -- No special care has to be taken to support
+                    -- writing and shifting at the same time.
+                    
+                    if v_shift = '1' then
+                        hex_register(63 downto 56) <= (others => '0');
+                        hex_register(55 downto 0) <= hex_register(63 downto 8);
+                    end if;
+                        
+                    if v_write = '1' then
+                        hex_register(59 downto 56) <= v_data;
+                        hex_register(60) <= not v_off; -- unclear if this should only be set when write is 1
+                    end if;
+
+                    if v_clear = '1' then
+                        hex_register <= (others => '0');    
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process(clk)
+    begin
+        if clk'event and clk='1' then
+            if rst = '1' then
+                hex <= hex_register(4 downto 0);
+                anodes <= (others => not '0');
+                overflow_counter <= 0;
+            else
+                if timer_overflow = '1' then
+                    if overflow_counter = 7 then
+                        overflow_counter <= 0;
+                    else
+                        overflow_counter <= overflow_counter + 1;
+                    end if;
+
+                    anodes <= (others => not '0');
+                    anodes(overflow_counter) <= not '1';
+                    
+                    hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
+                end if;
+            end if;
+        end if;
+    end process;
+
+	wslvo.dat <= data_out;
+
+	wslvo.ack	<= ack;
+	wslvo.wbcfg	<= wb_membar(memaddr, addrmask);
+
+end Behavioral;

soc/peripheral/simple_timer.vhd

@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity simple_timer is
+    generic(
+        timer_start : std_logic_vector (31 downto 0)
+    );
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+        timer_overflow : out std_logic
+    );
+end entity simple_timer;
+
+architecture Behavioral of simple_timer is
+
+	signal counter : integer range 1 to to_integer(unsigned(timer_start));
+    signal overflow : std_logic;
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				counter <= to_integer(unsigned(timer_start));
+			else
+                overflow <= '0';
+
+				if counter = 1 then
+                    counter <= to_integer(unsigned(timer_start));
+                    overflow <= '1';
+                else
+                    counter <= counter - 1;
+                end if;
+			end if;
+		end if;
+	end process;
+
+    timer_overflow <= overflow;
+
+end Behavioral;

soc/peripheral/switches.vhd

@@ -0,0 +1,88 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+
+entity wb_switches is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_SW;
+		addrmask	:	generic_mask_type --:= CFG_MADR_SW;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        buttons : in std_logic_vector(4 downto 0);
+        switches : in std_logic_vector(15 downto 0);
+
+        interrupt : out std_logic
+	);
+end wb_switches;
+
+architecture Behavioral of wb_switches is
+
+	signal data : std_logic_vector(20 downto 0);
+	signal ack	: std_logic;
+
+    signal old_input : std_logic_vector(20 downto 0);
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				ack		<= '0';
+				data	<= (others=>'0');
+			else
+				if wslvi.stb = '1' and wslvi.cyc = '1' then
+				    if wslvi.we='0' then
+                        data(15 downto 0) <= switches;
+                        data(20 downto 16) <= buttons;
+                    end if;
+				
+					if ack = '0' then
+						ack	<= '1';
+					else
+						ack	<= '0';
+					end if;
+				else
+					ack <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+    process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+                interrupt <= '0';
+                old_input <= buttons & switches;
+            else
+                if buttons & switches /= old_input
+                then
+                    interrupt <= '1';
+                else
+                    interrupt <= '0';
+                end if;
+
+                old_input(15 downto 0) <= switches;
+                old_input(20 downto 16) <= buttons;
+            end if;
+        end if;
+    end process;
+
+	wslvo.dat(20 downto 0)	<= data;
+	wslvo.dat(31 downto 21)	<= (others=>'0');
+
+	wslvo.ack	<= ack;
+	wslvo.wbcfg	<= wb_membar(memaddr, addrmask);
+
+end Behavioral;

soc/peripheral/timer.vhd

@@ -0,0 +1,140 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+
+entity wb_timer is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_TIMER;
+		addrmask	:	generic_mask_type --:= CFG_MADR_TIMER;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        interrupt : out std_logic
+	);
+end wb_timer;
+
+architecture Behavioral of wb_timer is
+	constant TARGET_COUNT_DEFAULT   : integer := 32 - 1;
+	
+	signal ack	: std_logic;
+
+	signal counter : integer range 0 to 65535;
+	signal counter_target_value : integer range 0 to 65535;
+
+	signal enable : std_logic;
+	signal repeat : std_logic;
+	signal reset : std_logic;
+
+	signal counter_vector : std_logic_vector(31 downto 0);
+	signal status_register : std_logic_vector(31 downto 0);
+	
+	signal data_in : std_logic_vector(2 downto 0);
+	signal data_in_changed : std_logic;
+
+begin
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				counter <= 0;
+			else
+			    if reset = '1' then -- reset register
+			         counter <= 0;
+			    else			
+                    if enable = '1' then
+                        if counter = counter_target_value then
+                            counter <= 0;
+                        else
+                            counter <= counter + 1;
+                        end if;
+                    end if;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	process(clk)
+	begin
+        if clk'event and clk='1' then
+			if rst = '1' then
+				enable <= '0';
+				repeat <= '0';
+				reset <= '0';
+			else
+			     reset <= '0';
+			     
+			     if data_in_changed = '1' then
+                     enable <= data_in(0);
+                     repeat <= data_in(1);
+                     reset <= data_in(2);
+			     end if;
+			
+			     -- Reset enable bit
+			     if counter = counter_target_value and repeat = '0' then
+			         enable <= '0';
+			     end if;
+		    end if;
+		end if;
+	end process;
+
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				ack	<= '0';
+				data_in <= (others => '0');
+				data_in_changed <= '0';
+				counter_target_value <= TARGET_COUNT_DEFAULT;
+			else
+			    data_in <= (others => '0');
+			    data_in_changed <= '0';
+			    
+				if wslvi.stb = '1' and wslvi.cyc = '1' then
+				    if wslvi.we='1' and wslvi.adr(2) = '1' then
+				        data_in <= dec_wb_dat(wslvi.sel,wslvi.dat)(2 downto 0);
+				        data_in_changed <= '1';
+				    end if;
+				    
+                    if wslvi.we='1' and wslvi.adr(2) = '0' then
+				        counter_target_value <= to_integer(unsigned(dec_wb_dat(wslvi.sel,wslvi.dat)));
+				    end if;
+				
+					if ack = '0' then
+						ack	<= '1';
+					else
+						ack	<= '0';
+					end if;
+				else
+					ack <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+	counter_vector <= std_logic_vector(to_unsigned(counter_target_value, counter_vector'length));
+	
+	status_register(0) <= enable; -- enable
+	status_register(1) <= repeat; -- repeat
+	status_register(31 downto 2) <= (others => '0'); -- reset bit always reads as 0
+
+	wslvo.dat <= counter_vector when wslvi.adr(2) = '0'
+	   else status_register when wslvi.adr(2) = '1'
+	   else (others => '0');
+		
+	interrupt <= '1' when counter = counter_target_value else '0';
+
+	wslvo.ack	<= ack;
+	wslvo.wbcfg	<= wb_membar(memaddr, addrmask);
+
+end Behavioral;

soc/testbench/can_demo_tb.vhd

@@ -111,13 +111,13 @@ begin
 		
 
 		--setup both can nodes
-		write_regs_from_file( "./testdata/default_setup.tdf", wbs_i1, wbs_o1, clk);
+		write_regs_from_file( "/home/derek/Git/lt16lab/soc/testbench/testdata/default_setup.tdf", wbs_i1, wbs_o1, clk);
 		--wait for 1000 ns;
-		write_regs_from_file( "./testdata/default_setup.tdf", wbs_i2, wbs_o2, clk);
+		write_regs_from_file( "/home/derek/Git/lt16lab/soc/testbench/testdata/default_setup.tdf", wbs_i2, wbs_o2, clk);
 		
 		wait for 1000 ns;
 		--setup and execute a 2 byte transmission in controller 1
-		write_regs_from_file( "./testdata/data_send.tdf", wbs_i1, wbs_o1, clk);
+		write_regs_from_file( "/home/derek/Git/lt16lab/soc/testbench/testdata/data_send.tdf", wbs_i1, wbs_o1, clk);
 		tx_vector(2) <= tx_vector(1);
 		
 		--manual ack by copying controler 2's ack
@@ -131,7 +131,7 @@ begin
 		--read status register of controller 1
 		can_wb_read_reg(wbs_i1, wbs_o1, 2, clk);
 		--read from controller 2's read buffer
-		read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data0.tdf", wbs_i2, wbs_o2, clk);
+		read_regs_with_fileaddr("/home/derek/Git/lt16lab/soc/testbench/testdata/data_read.tdf", "read_data0.tdf", wbs_i2, wbs_o2, clk);
 		
 		wait for 1200 ns;
 		--release receive buffer of controller 2
@@ -146,8 +146,8 @@ begin
 		wait on irq_on2;
 		
 		--read from both receive buffers
-		read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data1.tdf", wbs_i1, wbs_o1, clk);
+		read_regs_with_fileaddr("/home/derek/Git/lt16lab/soc/testbench/testdata/data_read.tdf", "read_data1.tdf", wbs_i1, wbs_o1, clk);
-		read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data2.tdf", wbs_i2, wbs_o2, clk);
+		read_regs_with_fileaddr("/home/derek/Git/lt16lab/soc/testbench/testdata/data_read.tdf", "read_data2.tdf", wbs_i2, wbs_o2, clk);
 		wait for 2400 ns;
 		--release both receive buffers
 		can_wb_write_reg(wbs_i1, wbs_o1, 1, "00000100", clk);

soc/testbench/hex2physical_tb.vhd

@@ -0,0 +1,88 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+
+ENTITY hex2physical_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF hex2physical_tb IS
+
+	signal hex : std_logic_vector(4 downto 0) := "00000";
+    signal cathodes : std_logic_vector(7 downto 0);
+
+    component hex2physical
+    port(
+        hex : in std_logic_vector(4 downto 0);
+        cathodes : out std_logic_vector(7 downto 0)
+    );
+    end component;
+
+BEGIN
+
+	converter: hex2physical
+        port map(
+			hex => hex,
+            cathodes => cathodes
+		);
+
+	stimuli: process
+	begin		
+        hex <= "00000";
+		wait for 2 ns;
+
+        hex <= "00001";
+		wait for 2 ns;
+
+        hex <= "00010";
+		wait for 2 ns;
+
+        hex <= "00011";
+		wait for 2 ns;
+
+        hex <= "00100";
+		wait for 2 ns;
+
+        hex <= "00101";
+		wait for 2 ns;
+
+        hex <= "00110";
+		wait for 2 ns;
+
+        hex <= "00111";
+		wait for 2 ns;
+
+        hex <= "01000";
+		wait for 2 ns;
+
+        hex <= "01001";
+		wait for 2 ns;
+
+        hex <= "01010";
+		wait for 2 ns;
+
+        hex <= "01011";
+		wait for 2 ns;
+
+        hex <= "01100";
+		wait for 2 ns;
+
+        hex <= "01101";
+		wait for 2 ns;
+
+        hex <= "01110";
+		wait for 2 ns;
+
+        hex <= "01111";
+		wait for 2 ns;
+
+        hex <= "10000";
+		wait for 2 ns;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/project.vhd

@@ -0,0 +1,111 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
+ENTITY project_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF project_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+    
+	constant peer_num_inst : integer := 3;
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>rx_vector(0),
+        can_tx_o=>tx_vector(0)
+	);
+	 
+    can_inst_2 : can_vhdl_top
+    generic map(
+        memaddr=>CFG_BADR_MEM,
+        addrmask=>CFG_MADR_FULL
+    )
+    port map(
+        clk	=> clk,
+        rstn	=> rst,
+        wbs_i	=> wbs_i2,
+        wbs_o	=> wbs_o2,
+        rx_i	=> rx_vector(1),
+        tx_o	=> tx_vector(1),
+        irq_on	=> irq_on2
+    );
+        
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => 2
+    )
+    port map(
+        rst => rst,
+        rx_vector => can_rx,
+        tx_vector => can_tx
+    );
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 300us;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/project_2top.vhd

@@ -0,0 +1,158 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
+ENTITY project_2top_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF project_2top_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led0	: std_logic_vector(7 downto 0);
+    signal led1	: std_logic_vector(7 downto 0);
+    signal btn0 : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn1 : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes0 : std_logic_vector(7 downto 0);
+    signal cathodes0 : std_logic_vector(7 downto 0);
+    signal anodes1 : std_logic_vector(7 downto 0);
+    signal cathodes1 : std_logic_vector(7 downto 0);
+    signal rst_n : std_logic;
+    
+	constant peer_num_inst : integer := 2;
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	
+	signal de : std_logic_vector(1 downto 0);
+	signal re_n : std_logic_vector(1 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project_sim.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            pmod_rxd : in std_logic;
+            pmod_txd : out std_logic;
+            pmod_de : out std_logic;
+            pmod_re_n : out std_logic
+		);
+	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
+
+BEGIN
+
+	soc0: lt16soc_top
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led0,
+		btn=>btn0,
+		sw=>sw,
+        anodes=>anodes0,
+        cathodes=>cathodes0,
+        pmod_rxd => rx_vector(0),
+        pmod_txd => tx_vector(0),
+        pmod_de => de(0),
+        pmod_re_n => re_n(0)
+	);
+
+    soc1: lt16soc_top
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led1,
+		btn=>btn1,
+		sw=>sw,
+        anodes=>anodes1,
+        cathodes=>cathodes1,
+        pmod_rxd => rx_vector(1),
+        pmod_txd => tx_vector(1),
+        pmod_de => de(1),
+        pmod_re_n => re_n(1)
+	);
+        
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => peer_num_inst
+    )
+    port map(
+        rst => rst_n,
+        rx_vector => rx_vector,
+        tx_vector => tx_vector
+    );
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		sw <= x"000F";
+		
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		
+		wait for 3us;
+		-- btn0 <= "00100"; -- freq
+		btn0 <= "00001"; -- add
+		-- btn0 <= "00010"; -- clear
+		
+		wait for 50us;
+		sw <= x"000A";
+		btn0 <= "00000";
+		btn1 <= "00001"; -- add		
+		
+		--wait for 50us;
+		--btn0 <= "00100"; -- freq
+		
+        wait for 50us;
+        sw <= x"1550";
+        btn0 <= "00000";
+		btn1 <= "00100"; -- freq
+		
+		wait for 500us;
+		btn0 <= "00010"; -- clear
+		
+        wait for 50us;
+		sw <= x"000C";
+		btn0 <= "00000";
+		btn1 <= "00001"; -- add	
+		
+        wait for 50us;
+		btn1 <= "00010"; -- clear
+				
+		wait for 100us;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+	
+	rst_n <= not rst;
+
+END ARCHITECTURE;

soc/testbench/scrolling_buffer_tb.vhd

@@ -0,0 +1,177 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+
+ENTITY scrolling_buffer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF scrolling_buffer_tb IS
+
+    constant CLK_PERIOD : time := 10 ns;
+
+    signal rst : std_logic;
+    signal clk : std_logic := '0';
+
+    signal buffer_clear : std_logic := '0';
+    signal buffer_write : std_logic := '0';
+    signal buffer_data : std_logic_vector(4 downto 0) := (others => '0');
+    signal next_char : std_logic := '0';
+    signal hex_char : std_logic_vector(4 downto 0);
+
+    component scrolling_buffer
+        port(
+            clk : in std_logic;
+            rst : in std_logic;
+            buffer_clear : in std_logic;
+            buffer_write : in std_logic;
+            buffer_data : in std_logic_vector(4 downto 0);
+            next_char : in std_logic;
+            hex_char : out std_logic_vector(4 downto 0)
+        );
+    end component;
+
+BEGIN
+
+	buf: scrolling_buffer
+        port map(
+			clk => clk,
+            rst => rst,
+            buffer_clear => buffer_clear,
+            buffer_write => buffer_write,
+            buffer_data => buffer_data,
+            next_char => next_char,
+            hex_char => hex_char
+    );
+
+    clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+        rst <= '1';
+        wait for CLK_PERIOD;
+
+        rst <= '0';
+        wait for CLK_PERIOD;
+
+        buffer_data <= "00001";
+        buffer_write <= '1';
+        
+        wait for CLK_PERIOD;
+        buffer_data <= "01011";
+        
+        wait for CLK_PERIOD;
+        buffer_write <= '0';
+        
+        wait for CLK_PERIOD;
+        buffer_data <= "01001";
+        buffer_write <= '1';
+        
+        wait for CLK_PERIOD;
+        buffer_data <= "00000";
+        buffer_write <= '0';
+        
+        wait for CLK_PERIOD;
+        next_char <= '1';
+        
+        wait for CLK_PERIOD;
+        assert hex_char = "00001" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = "01011" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = "01001" severity failure;
+        
+        wait for CLK_PERIOD;
+        next_char <= '0';
+        assert hex_char = "00001" severity failure; -- special case
+
+        wait for CLK_PERIOD * 3;
+        
+        -- Write buffer full
+        buffer_data <= "11111";
+        buffer_write <= '1';
+        
+        wait for CLK_PERIOD * 16;
+        buffer_data <= "00000";
+        buffer_write <= '0';
+        
+        wait for CLK_PERIOD;
+        next_char <= '1';
+
+		wait for CLK_PERIOD * 8;
+		buffer_clear <= '1';
+		next_char <= '0';
+		
+		wait for CLK_PERIOD;
+		buffer_clear <= '0';
+        buffer_data <= '0' & x"D";
+        buffer_write <= '1';
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"E";
+    
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"A";
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"D";
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"B";
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"E";
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"E";
+
+        wait for CLK_PERIOD;
+		buffer_data <= '0' & x"F";
+
+        wait for CLK_PERIOD;
+        buffer_data <= (others => '0');
+		buffer_write <= '0';
+		
+        wait for CLK_PERIOD;
+        wait for CLK_PERIOD;
+        next_char <= '1';
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"D" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"E" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"A" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"D" severity failure;
+
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"B" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"E" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"E" severity failure;
+        
+        wait for CLK_PERIOD;
+        assert hex_char = '0' & x"F" severity failure;
+
+		wait for CLK_PERIOD * 8;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/scrolling_controller_tb.vhd

@@ -0,0 +1,102 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+
+ENTITY scrolling_controller_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF scrolling_controller_tb IS
+
+    constant CLK_PERIOD : time := 10 ns;
+
+    signal rst : std_logic;
+    signal clk : std_logic := '0';
+
+    signal on_off : std_logic := '0';
+    signal cnt_start : std_logic := '0';
+    signal cnt_done : std_logic := '0';
+    signal next_char : std_logic := '0';
+    signal hex_char : std_logic_vector(4 downto 0) := (others => '0');
+    signal seg_data : std_logic_vector(3 downto 0) := (others => '0');
+    signal seg_off : std_logic := '0';
+    signal seg_shift : std_logic := '0';
+    signal seg_write : std_logic := '0';
+    signal seg_clear : std_logic := '0';
+
+    component scrolling_controller
+        port(
+            clk : in std_logic;
+            rst : in std_logic;
+            on_off : in std_logic;
+            cnt_start : out std_logic;
+            cnt_done : in std_logic;
+            next_char : out std_logic;
+            hex_char : in std_logic_vector(4 downto 0);
+            seg_data : out std_logic_vector(3 downto 0);
+            seg_off : out std_logic;
+            seg_shift : out std_logic;
+            seg_write : out std_logic;
+            seg_clear : out std_logic
+        );
+    end component;
+BEGIN
+
+	controller: scrolling_controller
+        port map(
+			clk => clk,
+            rst => rst,
+            on_off => on_off,
+            cnt_start => cnt_start,
+            cnt_done => cnt_done,
+            next_char => next_char,
+            hex_char => hex_char,
+            seg_data => seg_data,
+            seg_off => seg_off,
+            seg_shift => seg_shift,
+            seg_write => seg_write,
+            seg_clear => seg_clear
+    );
+
+    clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+        rst <= '1';
+        wait for CLK_PERIOD;
+
+        rst <= '0';
+        wait for CLK_PERIOD;
+
+        hex_char <= "01010";
+
+        wait for CLK_PERIOD * 2;
+        on_off <= '1';
+
+        wait for CLK_PERIOD;
+        on_off <= '0';
+
+        wait for CLK_PERIOD*3;
+        hex_char <= "00101";
+        cnt_done <= '1';
+
+        wait for CLK_PERIOD;
+        cnt_done <= '0';
+
+        wait for CLK_PERIOD * 3;
+        on_off <= '1';
+        hex_char <= "01111";
+
+        wait for CLK_PERIOD * 5;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/scrolling_timer_tb.vhd

@@ -0,0 +1,77 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+
+ENTITY scrolling_timer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF scrolling_timer_tb IS
+
+    constant CLK_PERIOD : time := 10 ns;
+
+    signal rst : std_logic;
+    signal clk : std_logic := '0';
+
+	signal cnt_start : std_logic := '0';
+    signal cnt_done : std_logic := '0';
+    signal cnt_value : std_logic_vector(31 downto 0) := x"00000000";
+
+    component scrolling_timer is
+        port(
+            clk : in std_logic;
+            rst : in std_logic;
+            cnt_start : in std_logic;
+            cnt_done : out std_logic;
+            cnt_value : in std_logic_vector(31 downto 0)
+        );
+    end component;
+
+BEGIN
+
+	timer: scrolling_timer
+        port map(
+			clk => clk,
+            rst => rst,
+            cnt_start => cnt_start,
+            cnt_done => cnt_done,
+            cnt_value => cnt_value
+    );
+
+    clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+        rst <= '1';
+        wait for CLK_PERIOD;
+        rst <= '0';
+
+        wait for CLK_PERIOD*3;
+
+        cnt_value <= x"00000100";
+        cnt_start <= '1';
+        
+        wait for CLK_PERIOD;
+        cnt_start <= '0';
+
+		wait for CLK_PERIOD * 300;
+
+        cnt_value <= x"0000000A";
+        cnt_start <= '1';
+        
+        wait for CLK_PERIOD;
+        cnt_start <= '0';
+        
+        wait for CLK_PERIOD * 15;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/scrolling_top_tb.vhd

@@ -0,0 +1,262 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY scrolling_top_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF scrolling_top_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0) := (others => '0');
+	
+    signal anodes: std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+	signal slvi	: wb_slv_in_type;
+	signal slvo	: wb_slv_out_type;
+
+BEGIN
+
+	SIM_SLV: wb_scrolling
+		generic map(
+			memaddr		=> CFG_BADR_SCR,
+			addrmask	=> CFG_MADR_SCR
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			anodes => anodes,
+			cathodes => cathodes,
+			wslvi	=> slvi,
+			wslvo	=> slvo
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD / 2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+        
+		wait for CLK_PERIOD;
+		
+        -- Set cnt_value
+        data <= x"00000100";
+		generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
+		
+		wait for 2 ns;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"D"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"A"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+				
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"D"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(0) <= '1'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+		data <= (others => '0');
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		
+		wait for 100 us;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"B"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+				
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"F"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        wait for 100 us;
+        
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"B"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"A"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+				
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"D"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '1' & x"0"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"C"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"A"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+				
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"F"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+        data(8) <= '0'; -- buffer_clear
+        data(0) <= '0'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        wait for 100 us;
+
+        data <= (others => '0');
+        data(0) <= '1'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data <= (others => '0');
+        data(8) <= '1'; -- buffer_clear
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data <= (others => '0');
+        data(24) <= '1'; -- buffer_write
+        data(20 downto 16) <= '0' & x"D"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+		
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"A"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"D"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"B"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"E"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data(20 downto 16) <= '0' & x"F"; -- buffer_data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        data <= (others => '0');
+        data(0) <= '1'; -- on_off
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		wait for CLK_PERIOD;
+
+        wait for 100 us;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/segment_adv_tb.vhd

@@ -0,0 +1,125 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY segment_adv_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF segment_adv_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	signal data	: std_logic_vector(31 downto 0);
+	
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+	signal slvi	: wb_slv_in_type;
+	signal slvo	: wb_slv_out_type;
+
+BEGIN
+
+	SIM_SLV: wb_segment_adv
+		generic map(
+			memaddr		=> CFG_BADR_SEG,
+			addrmask	=> CFG_MADR_SEG
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			wslvi	=> slvi,
+			wslvo	=> slvo,
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+
+        data <= (others => '0');
+        data(24) <= '0'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '1'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"F"; -- data
+		generate_sync_wb_single_write(slvi,slvo,clk,data);
+		
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '1'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '0'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"0"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+		
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '1'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '1'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"A"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+        
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '1'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '1'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"B"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+        
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '1'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '1'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"C"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+        
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '1'; -- shift
+        data(16) <= '0'; -- clear
+        data(8) <= '1'; -- write
+        data(4) <= '1'; -- off
+        data(3 downto 0) <= x"0"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+        
+        wait for 1 us;
+        data <= (others => '0');
+        data(24) <= '0'; -- shift
+        data(16) <= '1'; -- clear
+        data(8) <= '0'; -- write
+        data(4) <= '0'; -- off
+        data(3 downto 0) <= x"0"; -- data
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+		
+		wait for 1 us;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/segment_tb.vhd

@@ -0,0 +1,206 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY segment_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF segment_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	
+    signal seg_data : std_logic_vector(3 downto 0) := (others => '0');
+    signal seg_off : std_logic := '0';
+    signal seg_shift : std_logic := '0';
+    signal seg_write : std_logic := '0';
+    signal seg_clear : std_logic := '0';   
+	
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+    component seven_segment_display is
+		port(
+            clk		: in  std_logic;
+            rst		: in  std_logic;
+            seg_data : in std_logic_vector(3 downto 0);
+            seg_off : in std_logic;
+            seg_shift : in std_logic;
+            seg_write : in std_logic;
+            seg_clear : in std_logic;   
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+		);
+	end component;
+
+BEGIN
+
+	SIM_SLV: seven_segment_display
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+            seg_data => seg_data,
+            seg_off => seg_off,
+            seg_shift => seg_shift,
+            seg_write => seg_write,
+            seg_clear => seg_clear,
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+
+        seg_shift <= '0'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"F"; -- data
+
+		wait for 1 us;
+		
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '0'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"0"; -- data
+        
+        wait for CLK_PERIOD;
+        seg_shift <= '0';
+		
+        wait for 1 us;
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"A"; -- data
+        
+        wait for CLK_PERIOD;
+        seg_shift <= '0';
+        
+        wait for 1 us;
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"B"; -- data
+
+        wait for CLK_PERIOD;
+        seg_shift <= '0';
+        
+        wait for 1 us;
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"C"; -- 
+        
+        wait for CLK_PERIOD;
+        seg_shift <= '0';        
+        
+        wait for 1 us;
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '1'; -- off
+        seg_data <= x"0"; -- data
+        
+        wait for CLK_PERIOD;
+        seg_shift <= '0';        
+        
+        wait for 1 us;
+        seg_shift <= '0'; -- shift
+        seg_clear <= '1'; -- clear
+        seg_write <= '0'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"0"; -- data
+		
+		wait for 1 us;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"D"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"E"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"A"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"D"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"B"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"E"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"E"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '1'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '1'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"F"; -- data
+        wait for CLK_PERIOD;
+
+        seg_shift <= '0'; -- shift
+        seg_clear <= '0'; -- clear
+        seg_write <= '0'; -- write
+        seg_off <= '0'; -- off
+        seg_data <= x"F"; -- data
+
+        wait for 1 us;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/simple_timer_tb.vhd

@@ -0,0 +1,58 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+
+ENTITY simple_timer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF simple_timer_tb IS
+
+    constant CLK_PERIOD : time := 10 ns;
+
+    signal rst : std_logic;
+    signal clk : std_logic := '0';
+	signal overflow : std_logic;
+
+    component simple_timer
+        generic(
+            timer_start : std_logic_vector (31 downto 0)
+        );
+        port(
+            clk : in std_logic;
+            rst : in std_logic;
+            timer_overflow : out std_logic
+        );
+    end component;
+
+BEGIN
+
+	timer: simple_timer
+        generic map (timer_start => x"0000001F")
+        port map(
+			clk => clk,
+            rst => rst,
+            timer_overflow => overflow
+    );
+
+    clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+        rst <= '1';
+        wait for CLK_PERIOD;
+        rst <= '0';
+
+		wait for 5 us;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/switches_interrupt_tb.vhd

@@ -0,0 +1,76 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY switches_interrupt_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF switches_interrupt_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+    signal can_tx_o : std_logic;
+    signal can_rx_i : std_logic := '0';
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/interrupt_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_tx_o : out std_logic;
+            can_rx_i : in std_logic
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>can_rx_i,
+        can_tx_o=>can_tx_o
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		
+		wait for 1us;
+		sw <= x"ACAB";
+		
+		wait for 1us;
+		
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/switches_tb.vhd

@@ -0,0 +1,109 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY switches_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF switches_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0);
+	
+    signal buttons: std_logic_vector(4 downto 0);
+    signal switches : std_logic_vector(15 downto 0);
+
+    signal interrupt : std_logic;
+
+	signal slvi	: wb_slv_in_type;
+	signal slvo	: wb_slv_out_type;
+
+BEGIN
+
+	SIM_SLV: wb_switches
+		generic map(
+			memaddr		=> CFG_BADR_LED,
+			addrmask	=> CFG_MADR_LED
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			buttons => buttons,
+			switches => switches,
+            interrupt => interrupt,
+			wslvi	=> slvi,
+			wslvo	=> slvo
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+		buttons <= "00110";
+		switches <= "1001000101010111";
+		wait for CLK_PERIOD;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data);
+		
+		wait for 2 ns;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data);
+		
+		buttons <= "11011";
+		switches <= x"DEAD";
+        wait for 10 ns;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "00"); -- Single byte
+		
+        wait for 10 ns;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "01"); -- Half word
+		
+		wait for 100 ns;
+		
+		buttons <= "00000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00100";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00000";
+		switches <= x"DAAD";
+		
+		wait for 50ns;
+		buttons <= "01000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00010";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/testdata/data_read.tdf

@@ -0,0 +1,4 @@
+20
+21
+22
+23

soc/testbench/testdata/data_send.tdf

@@ -0,0 +1,5 @@
+10 10101010
+11 11000010
+12 10101010
+13 00001111
+1 00000001

soc/testbench/testdata/default_setup.tdf

@@ -0,0 +1,6 @@
+4 00000000
+5 11111111
+6 10000000
+7 01001000
+8 00000010
+0 11111110

soc/testbench/timer_tb.vhd

@@ -0,0 +1,104 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY timer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF timer_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0);
+	
+    signal interrupt : std_logic;
+
+	signal slvi	: wb_slv_in_type;
+	signal slvo	: wb_slv_out_type;
+
+BEGIN
+
+	SIM_SLV: wb_timer
+		generic map(
+			memaddr		=> CFG_BADR_TIMER,
+			addrmask	=> CFG_MADR_TIMER
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			wslvi	=> slvi,
+			wslvo	=> slvo,
+			interrupt => interrupt
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		wait for CLK_PERIOD;
+		wait for CLK_PERIOD;
+		
+		-- Configure timer...
+		data	<= (others => '0');
+		data(0) <= '1'; -- enable
+		data(1) <= '1'; -- repeat
+		generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
+		
+		wait until interrupt = '1';
+		wait for CLK_PERIOD*20;
+		
+        -- Read counter value
+        data	<= (others => '0');
+		generate_sync_wb_single_read(slvi,slvo,clk,data);
+		
+		wait for CLK_PERIOD*4;
+		
+		-- Disable repeat and reset timer...
+        data	<= (others => '0');
+        data(1) <= '0'; -- repeat
+		data(2) <= '1'; -- reset
+		generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
+		
+		wait until interrupt = '1';
+		wait for CLK_PERIOD*20;
+		
+        -- Restart timer...
+        data	<= (others => '0');
+        data(0) <= '1'; -- enable
+        generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
+        
+        wait for CLK_PERIOD*20;
+        
+        -- Change target value
+        data <= std_logic_vector(to_unsigned(1024, data'length));
+        generate_sync_wb_single_write(slvi,slvo,clk,data);
+        
+        -- Read status register
+        data	<= (others => '0');
+        generate_sync_wb_single_read(slvi,slvo,clk,data, ADR_OFFSET => 4);
+        
+        wait until interrupt = '1';
+        wait for CLK_PERIOD * 5;
+        assert false report "Simulation terminated!" severity failure;
+
+		wait;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/warmup2.vhd

@@ -0,0 +1,65 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup2_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup2_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0);
+    signal sw : std_logic_vector(15 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/assignment2code.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		btn <= (others => '0');
+		sw <= (others => '0');
+		wait for 2000*CLK_PERIOD;
+		sw(2) <= '1';
+		wait for 2000*CLK_PERIOD;
+        btn <= (others => '1');
+		wait for 2000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/warmup2_timer.vhd

@@ -0,0 +1,59 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup2_timer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup2_timer_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/timer_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 2000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/warmup2_timer_blinky.vhd

@@ -0,0 +1,59 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup2_timer_blinky_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup2_timer_blinky_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/timer_blinky.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 20000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/warmup3.vhd

@@ -0,0 +1,65 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup3_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup3_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/segments_adv_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 5000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/warmup4.vhd

@@ -0,0 +1,65 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup4_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup4_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/interrupt_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 5ms;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/top/external_can.vhd

@@ -0,0 +1,129 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/04/2023 01:55:04 PM
+-- Design Name: 
+-- Module Name: internal_can - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity external_can is
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    -- pmod
+    pmod_rxd : in std_logic_vector(1 downto 0);
+    pmod_txd : out std_logic_vector(1 downto 0);
+    pmod_de : out std_logic_vector(1 downto 0);
+    pmod_re_n : out std_logic_vector(1 downto 0)
+);
+end entity;
+
+architecture Behavioral of external_can is
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
+	signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
+	
+	signal anodes_cpy : std_logic_vector(7 downto 0);
+    signal cathodes_cpy : std_logic_vector(7 downto 0);
+    
+    signal led_cpy : std_logic_vector(7 downto 0);
+    
+    signal tx : std_logic_vector(1 downto 0);
+    
+    signal rst_n : std_logic;
+begin
+
+	soc0: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes_cpy,
+        cathodes=>cathodes_cpy,
+        can_rx_i=>pmod_rxd(0),
+        can_tx_o=>tx(0)
+	);
+
+    soc1: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led_cpy,
+		btn=>btn_cpy,
+		sw=>sw_cpy,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>pmod_rxd(1),
+        can_tx_o=>tx(1)
+	);
+    
+    -- TODO: für pmod !read enable auf low setzen
+    pmod_re_n <= (others => '0');
+    -- pmod_de <= (others => '1');
+    
+    pmod_de <= not tx;
+    pmod_txd <= tx;
+    
+    rst_n <= not rst;
+
+end Behavioral;

soc/top/internal_can.vhd

@@ -0,0 +1,143 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/04/2023 01:55:04 PM
+-- Design Name: 
+-- Module Name: internal_can - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity internal_can is
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    can_rx_i : in std_logic;
+    can_tx_o : out std_logic
+);
+end entity;
+
+architecture Behavioral of internal_can is
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
+	
+    constant peer_num_inst : integer := 2;
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	
+	signal rst_n : std_logic;
+	
+    signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
+	signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
+	
+	signal anodes_cpy : std_logic_vector(7 downto 0);
+    signal cathodes_cpy : std_logic_vector(7 downto 0);
+    
+    signal led_cpy : std_logic_vector(7 downto 0);
+begin
+
+	soc0: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>rx_vector(0),
+        can_tx_o=>tx_vector(0)
+	);
+
+    soc1: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led_cpy,
+		btn=>btn_cpy,
+		sw=>sw_cpy,
+        anodes=>anodes_cpy,
+        cathodes=>cathodes_cpy,
+        can_rx_i=>rx_vector(1),
+        can_tx_o=>tx_vector(1)
+	);
+	
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => peer_num_inst
+    )
+    port map(
+        rst => rst_n,
+        rx_vector => rx_vector,
+        tx_vector => tx_vector
+    );
+    
+    rst_n <= not rst;
+    can_tx_o <= tx_vector(1);
+    
+    -- TODO: für pmod !read enable auf low setzen
+
+end Behavioral;

soc/top/top.vhd

@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;
 
 entity lt16soc_top is
 generic(
-	programfilename : string := "../../programs/blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+	programfilename : string := "../../programs/project.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
 );
 port(
 	-- clock signal
@@ -22,7 +22,18 @@ port(
 	-- external reset button
 	rst		: in std_logic;
 	
-	led		: out std_logic_vector(7 downto 0)
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    pmod_rxd : in std_logic;
+    pmod_txd : out std_logic;
+    pmod_de : out std_logic;
+    pmod_re_n : out std_logic
 );
 end entity lt16soc_top;
 
@@ -34,7 +45,7 @@ architecture RTL of lt16soc_top is
 
 	signal rst_gen	: std_logic;
 
-	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1110_0000_0000_0001";
+	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1110_0000_0001";
 	constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
 
 	signal slvo	: wb_slv_out_vector := (others=> wbs_out_none);
@@ -51,6 +62,8 @@ architecture RTL of lt16soc_top is
 
 	signal irq_lines  : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others=>'0');
 
+    signal can_tx : std_logic;
+
 	--//////////////////////////////////////////////////////
 	-- components
 	--//////////////////////////////////////////////////////
@@ -174,12 +187,71 @@ begin
 		addrmask=>CFG_MADR_DMEM)
 	port map(clk,rst_gen,slvi(CFG_DMEM),slvo(CFG_DMEM));
 
+    can_inst : can_vhdl_top
+    generic map(
+        memaddr=>CFG_BADR_CAN,
+        addrmask=>CFG_MADR_CAN
+    )
+    port map(
+        clk	=> clk,
+        rstn	=> rst_gen,
+        wbs_i	=> slvi(CFG_CAN),
+        wbs_o	=> slvo(CFG_CAN),
+        rx_i	=> pmod_rxd,
+        tx_o	=> pmod_txd,
+        irq_on	=> irq_lines(4)
+    );
+
 	leddev : wb_led
 	generic map(
-		CFG_BADR_LED,CFG_MADR_LED
+		CFG_BADR_LED,
+        CFG_MADR_LED
 	)
 	port map(
-		clk,rst_gen,led,slvi(CFG_LED),slvo(CFG_LED)
+		clk,
+        rst_gen,
+        led,
+        slvi(CFG_LED),
+        slvo(CFG_LED)
 	);
+	
+    swdev : wb_switches
+	generic map(
+		CFG_BADR_SW,CFG_MADR_SW
+	)
+	port map(
+		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw, irq_lines(3)
+	);
+	
+    timerdev : wb_timer
+	generic map(
+		CFG_BADR_TIMER,
+        CFG_MADR_TIMER
+	)
+	port map(
+		clk,
+        rst_gen,
+        slvi(CFG_TIMER),
+        slvo(CFG_TIMER)
+	);
+	
+    scrollingdev : wb_scrolling
+		generic map(
+			memaddr		=> CFG_BADR_SCR,
+			addrmask	=> CFG_MADR_SCR
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst_gen,
+			wslvi	=> slvi(CFG_SCR),
+			wslvo	=> slvo(CFG_SCR),
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
+
+    pmod_re_n <= '0';
+    pmod_de <= not can_tx;
+    pmod_txd <= can_tx;
 
 end architecture RTL;

soc/top/top.xdc

@@ -9,22 +9,22 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl
 
 
 ##Switches
-#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
-#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
-#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
-#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
-#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
-#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
-#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
-#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
-#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
-#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
+set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
-#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
-#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
-#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
-#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
-#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
-#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
 
 ## LEDs
 set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
@@ -53,48 +53,48 @@ set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led[7]
 #set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
 
 ##7 segment display
-#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { cathodes[7] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
-#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { cathodes[6] }]; #IO_25_14 Sch=cb
-#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { cathodes[5] }]; #IO_25_15 Sch=cc
-#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { cathodes[4] }]; #IO_L17P_T2_A26_15 Sch=cd
-#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { cathodes[3] }]; #IO_L13P_T2_MRCC_14 Sch=ce
-#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { cathodes[2] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
-#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { cathodes[1] }]; #IO_L4P_T0_D04_14 Sch=cg
-#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { cathodes[0] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
-#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { anodes[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
-#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { anodes[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
-#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { anodes[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
-#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { anodes[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
-#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { anodes[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
-#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { anodes[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
-#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { anodes[6] }]; #IO_L23P_T3_35 Sch=an[6]
-#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { anodes[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
 
 ##Buttons
 set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
-#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L9P_T1_DQS_14 Sch=btnc
-#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_D05_14 Sch=btnu
-#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L12P_T1_MRCC_14 Sch=btnl
-#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L10N_T1_D15_14 Sch=btnr
-#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { btn[4] }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
 
 
 ##Pmod Headers
 ##Pmod Header JA
-#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n }]; #IO_L20N_T3_A19_15 Sch=ja[1]
-#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { pmod_txd }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
-#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
-#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { pmod_de }]; #IO_L18N_T2_A23_15 Sch=ja[4]
 #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
 #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
 #set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
 #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
 
 ##Pmod Header JB
-#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
-#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { pmod_txd[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
-#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd[1] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
-#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { pmod_de[1] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
 #set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
 #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
 #set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]

soc/top/top_project.vhd

@@ -0,0 +1,257 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+library work;
+use work.lt16x32_internal.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
+entity lt16soc_top_project is
+generic(
+	programfilename : string := "../../programs/project.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+);
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    pmod_rxd : in std_logic;
+    pmod_txd : out std_logic;
+    pmod_de : out std_logic;
+    pmod_re_n : out std_logic
+);
+end entity lt16soc_top_project;
+
+
+architecture RTL of lt16soc_top_project is
+	--//////////////////////////////////////////////////////
+	-- constant & signal
+	--//////////////////////////////////////////////////////
+
+	signal rst_gen	: std_logic;
+
+	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1110_0000_0001";
+	constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
+
+	signal slvo	: wb_slv_out_vector := (others=> wbs_out_none);
+	signal msto	: wb_mst_out_vector := (others=> wbm_out_none);
+
+	signal slvi	: wb_slv_in_vector := (others=> wbs_in_none);
+	signal msti	: wb_mst_in_vector := (others=> wbm_in_none);
+
+	signal core2mem		: core_imem;
+	signal mem2core		: imem_core;
+
+	signal irq2core   : irq_core;
+	signal core2irq   : core_irq;
+
+	signal irq_lines  : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others=>'0');
+
+    signal can_tx : std_logic;
+
+	--//////////////////////////////////////////////////////
+	-- components
+	--//////////////////////////////////////////////////////
+
+	component corewrapper
+	port(
+		clk       : in  std_logic;
+		rst       : in  std_logic;
+
+		in_imem   : in	imem_core;
+		out_imem  : out	core_imem;
+
+		in_proc   : in  irq_core;
+		out_proc  : out core_irq;
+
+		hardfault : out std_logic;
+
+		wmsti	:	in	wb_mst_in_type;
+		wmsto	:	out	wb_mst_out_type
+	);
+	end component;
+
+	component irq_controller
+	port(
+		clk       : in  std_logic;
+		rst       : in  std_logic;
+
+		in_proc   : in  core_irq;
+		out_proc  : out irq_core;
+
+		irq_lines : in  std_logic_vector((2 ** irq_num_width) - 1 downto 0)
+	);
+	end component;
+
+	component wb_intercon
+	generic(
+		slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
+		mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000"
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		msti	: out wb_mst_in_vector;
+		msto	: in  wb_mst_out_vector;
+		slvi	: out wb_slv_in_vector;
+		slvo	: in  wb_slv_out_vector
+	);
+	end component;
+
+begin
+
+	with RST_ACTIVE_HIGH select rst_gen	<=
+		rst when true,
+		not rst when others;
+
+	--//////////////////////////////////////////////////////
+	-- Instantiate
+	--//////////////////////////////////////////////////////
+
+	corewrap_inst: corewrapper
+	port map(
+		clk => clk,
+        rst => rst_gen,
+
+		in_imem		=> mem2core,
+		out_imem	=> core2mem,
+
+		in_proc		=> irq2core,
+		out_proc	=> core2irq,
+
+		hardfault	=> irq_lines(1),
+		wmsti		=> msti(CFG_LT16),
+		wmsto		=> msto(CFG_LT16)
+
+	);
+
+	irqcontr_inst: irq_controller
+	port map(
+		clk			=>	clk,
+		rst			=>	rst_gen,
+		in_proc		=>	core2irq,
+		out_proc	=>	irq2core,
+		irq_lines	=>	irq_lines
+	);
+
+	wbicn_inst: wb_intercon
+	generic map(
+		slv_mask_vector => slv_mask_vector,
+		mst_mask_vector => mst_mask_vector
+	)
+	port map(
+          clk => clk,
+          rst => rst_gen,
+          msti => msti,
+          msto => msto,
+          slvi => slvi,
+          slvo => slvo
+	);
+
+	memwrap_inst: memwrapper
+	generic map(
+		memaddr		=> CFG_BADR_MEM,
+		addrmask	=> CFG_MADR_MEM,
+		filename	=> programfilename,
+		size		=> IMEMSZ
+	)
+	port map(
+		clk 		=> clk,
+        rst 		=> rst_gen,
+		in_imem		=> core2mem,
+		out_imem	=> mem2core,
+
+		fault		=> irq_lines(2),
+		wslvi		=> slvi(CFG_MEM),
+		wslvo		=> slvo(CFG_MEM)
+	);
+
+	dmem : wb_dmem
+	generic map(
+		memaddr=>CFG_BADR_DMEM,
+		addrmask=>CFG_MADR_DMEM)
+	port map(clk,rst_gen,slvi(CFG_DMEM),slvo(CFG_DMEM));
+
+    can_inst : can_vhdl_top
+    generic map(
+        memaddr=>CFG_BADR_CAN,
+        addrmask=>CFG_MADR_CAN
+    )
+    port map(
+        clk	=> clk,
+        rstn	=> rst_gen,
+        wbs_i	=> slvi(CFG_CAN),
+        wbs_o	=> slvo(CFG_CAN),
+        rx_i	=> pmod_rxd,
+        tx_o	=> pmod_txd,
+        irq_on	=> irq_lines(4)
+    );
+
+	leddev : wb_led
+	generic map(
+		CFG_BADR_LED,
+        CFG_MADR_LED
+	)
+	port map(
+		clk,
+        rst_gen,
+        led,
+        slvi(CFG_LED),
+        slvo(CFG_LED)
+	);
+	
+    swdev : wb_switches
+	generic map(
+		CFG_BADR_SW,CFG_MADR_SW
+	)
+	port map(
+		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw, irq_lines(3)
+	);
+	
+    timerdev : wb_timer
+	generic map(
+		CFG_BADR_TIMER,
+        CFG_MADR_TIMER
+	)
+	port map(
+		clk,
+        rst_gen,
+        slvi(CFG_TIMER),
+        slvo(CFG_TIMER)
+	);
+	
+    scrollingdev : wb_scrolling
+		generic map(
+			memaddr		=> CFG_BADR_SCR,
+			addrmask	=> CFG_MADR_SCR
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst_gen,
+			wslvi	=> slvi(CFG_SCR),
+			wslvo	=> slvo(CFG_SCR),
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
+
+    pmod_re_n <= '0';
+    pmod_de <= not can_tx;
+    pmod_txd <= can_tx;
+
+end architecture RTL;