Modify program to adapt for new register layout

programs/segments_adv_test.prog

@@ -0,0 +1,169 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+segment_addr: .word 0x000F00A0
+// w_cnt_top:  .word 0xFFC000
+w_cnt_top:    .word 0x100 //for simulation only
+
+write_and_shift:
+    .word 0x01000100
+
+main:
+    ldr r8, >w_cnt_top
+    ldr r0, >segment_addr
+    ldr r1, >write_and_shift
+
+number_loop:
+    // 0 1 2 3 4 5 6 7
+    clr r4
+    addi r4, 0x0
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x1
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x2
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x3
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x4
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x5
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x6
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x7
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 8 9 A B C D E F
+    clr r4
+    addi r4, 0x8
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0x9
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xA
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xB
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xC
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xF
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 0xDEADBEEF pattern:
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xA
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xD
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xB
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xE
+    or r4, r4, r1
+    st32 r0, r4
+
+    clr r4
+    addi r4, 0xF
+    or r4, r4, r1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    br always >number_loop
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+    inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

soc/testbench/warmup3.vhd

@@ -21,7 +21,7 @@ ARCHITECTURE sim OF warmup3_tb IS
 
 	COMPONENT lt16soc_top IS
 		generic(
-			programfilename : string := "../../programs/segments_test.ram"
+			programfilename : string := "../../programs/segments_adv_test.ram"
 		);
 		port(
 			clk		: in  std_logic;