92 lines
3.2 KiB
VHDL
92 lines
3.2 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package lt16x32_global is
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-- width of the memory, the core supports 32 only
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constant memory_width : integer := 32;
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-- width of the vector holding the interrupt number, maximum 7 due to processor architecture
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constant irq_num_width : integer := 5;
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-- width of the vector holding the interrupt priority, maximum 6 due to processor architecture
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constant irq_prio_width : integer := 4;
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-- collection of all signals from the core to the data memory
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type core_dmem is record
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-- data written to the memory
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write_data : std_logic_vector(memory_width - 1 downto 0);
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-- address to which the data is written
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write_addr : std_logic_vector(memory_width - 1 downto 0);
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-- size of the written data
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-- 00: byte (8bits)
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-- 01: halfword (16bits)
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-- 10: word (32bits)
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-- 11: longword (64bits, currently not featured)
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write_size : std_logic_vector(1 downto 0);
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-- write enable signal, active high
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write_en : std_logic;
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-- address from which data is read
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read_addr : std_logic_vector(memory_width - 1 downto 0);
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-- size of the read data
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-- 00: byte (8bits)
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-- 01: halfword (16bits)
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-- 10: word (32bits)
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-- 11: longword (64bits, currently not featured)
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read_size : std_logic_vector(1 downto 0);
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-- read enable signal, active high
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read_en : std_logic;
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end record;
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-- collection of all signals from the data memory to the core
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type dmem_core is record
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-- read data, right aligned and zero-filled
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read_data : std_logic_vector(memory_width - 1 downto 0);
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-- ready signal, high if read data is valid
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ready : std_logic;
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end record;
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-- collection of all signals from the core to the instruction memory
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type core_imem is record
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-- address from which the instruction should be read
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read_addr : std_logic_vector(memory_width - 1 downto 0);
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-- read enable signal, active high
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read_en : std_logic;
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end record;
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-- collection of all signals from the instruction memory to the core
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type imem_core is record
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-- read data
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read_data : std_logic_vector(memory_width - 1 downto 0);
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-- ready signal, high if read data is valid
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ready : std_logic;
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end record;
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-- collection of all signals from the interrupt controller to the core
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type irq_core is record
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-- interrupt number of requested interrupt
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num : unsigned(irq_num_width - 1 downto 0);
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-- priority of requested interrupt (higher number means higher priority)
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priority : unsigned(irq_prio_width - 1 downto 0);
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-- request signal, active high
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req : std_logic;
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-- non maskable interrupt flag, active high
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nmi : std_logic;
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end record;
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-- collection of all signals from the core to the interrupt controller
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type core_irq is record
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-- interrupt acknowledge, high if requested interrupt is processed
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ack : std_logic;
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-- number of interrupt requested by internal trap instruction
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trap_num : unsigned(irq_num_width - 1 downto 0);
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-- request signal for internal trap, active high
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trap_req : std_logic;
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end record;
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end package lt16x32_global;
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package body lt16x32_global is
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end package body lt16x32_global;
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