Integrate timer module in top and add test program

programs/timer_test.prog

@@ -0,0 +1,56 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+timer_interrupt:
+    br >timer_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+timer_counter_addr: .word 0x000F0008
+timer_status_addr: .word 0x000F000C
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FF
+priority_mask: .word 0xFFFFFF03
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    ldr r0,>led_addr                // LED addr
+    ldr r1,>timer_status_addr      // Timer addr
+
+    // Set some LEDs
+    clr r2
+    addi r2, 0x5A
+    st08 r0, r2
+
+    // Enable the timer...
+    clr r2
+    addi r2, 0x1 // enable bit set
+    st08 r1, r2
+
+loop:
+    call >loop
+    nop
+
+
+timer_interrupt_handler:
+    // Set LEDs to indicate we reached the timer interrupt
+    clr r2
+    addi r2, -1
+    st08 r0, r2
+    reti

soc/testbench/warmup2_timer.vhd

@@ -0,0 +1,59 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup2_timer_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup2_timer_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/timer_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 2000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/top/top.vhd

@@ -37,7 +37,7 @@ architecture RTL of lt16soc_top is
 
 	signal rst_gen	: std_logic;
 
-	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_0000_0000_0001";
+	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1000_0000_0001";
 	constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
 
 	signal slvo	: wb_slv_out_vector := (others=> wbs_out_none);
@@ -192,5 +192,13 @@ begin
 	port map(
 		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw
 	);
+	
+    timerdev : wb_timer
+	generic map(
+		CFG_BADR_TIMER,CFG_MADR_TIMER
+	)
+	port map(
+		clk,rst_gen,slvi(CFG_TIMER),slvo(CFG_TIMER), irq_lines(3)
+	);
 
 end architecture RTL;