derek/lt16lab
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Make timer target value configurable

Browse Source
This commit is contained in:
Derek Christ
2022-11-06 20:11:01 +01:00
parent c35376833f
commit 85112d9938
3 changed files with 24 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
programs/timer_blinky.prog
View File

@@ -21,7 +21,7 @@ timer_status_addr: .word 0x000F000C
dmem_start_addr: .word 0x00000400
dmem_end_addr: .word 0x000004FC
priority_mask: .word 0xFFFFFF03
xor_mask: .word 0xFFFFFFFF
timer_target_value: .word 127 // change for simulation / real board
main:
// Initialize stack pointer to the end of the data memory
@@ -33,6 +33,7 @@ main:
ldr r0,>led_addr // LED addr
ldr r1,>timer_status_addr // Timer addr
ldr r3,>timer_counter_addr // Timer addr
// Init
clr r9 // 0 if we are currently filling, 1 if we are currently flushing
@@ -42,6 +43,9 @@ main:
addi r4, 10
// Enable the timer...
ldr r2, >timer_target_value // target value
st32 r3, r2
clr r2
addi r2, 0x3 // enable and repeat bit set
st32 r1, r2

19
soc/peripheral/timer.vhd
View File

@@ -3,6 +3,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.lt16x32_global.all;
use work.wishbone.all;
use work.config.all;
@@ -23,11 +24,12 @@ entity wb_timer is
end wb_timer;
architecture Behavioral of wb_timer is
constant COUNT_MAX : integer := 128 - 1;
constant TARGET_COUNT_DEFAULT : integer := 32 - 1;
signal ack : std_logic;
signal counter : integer range 0 to COUNT_MAX;
signal counter : integer range 0 to 65535;
signal counter_target_value : integer range 0 to 65535;
signal enable : std_logic;
signal repeat : std_logic;
@@ -51,7 +53,7 @@ begin
counter <= 0;
else
if enable = '1' then
if counter = COUNT_MAX then
if counter = counter_target_value then
counter <= 0;
else
counter <= counter + 1;
@@ -79,7 +81,7 @@ begin
end if;
-- Reset enable bit
if counter = COUNT_MAX and repeat = '0' then
if counter = counter_target_value and repeat = '0' then
enable <= '0';
end if;
end if;
@@ -93,6 +95,7 @@ begin
ack <= '0';
data_in <= (others => '0');
data_in_changed <= '0';
counter_target_value <= TARGET_COUNT_DEFAULT;
else
data_in <= (others => '0');
data_in_changed <= '0';
@@ -102,6 +105,10 @@ begin
data_in <= dec_wb_dat(wslvi.sel,wslvi.dat)(2 downto 0);
data_in_changed <= '1';
end if;
if wslvi.we='1' and wslvi.adr(2) = '0' then
counter_target_value <= to_integer(unsigned(dec_wb_dat(wslvi.sel,wslvi.dat)));
end if;
if ack = '0' then
ack <= '1';
@@ -115,7 +122,7 @@ begin
end if;
end process;
counter_vector <= std_logic_vector(to_unsigned(counter, counter_vector'length));
counter_vector <= std_logic_vector(to_unsigned(counter_target_value, counter_vector'length));
status_register(0) <= enable; -- enable
status_register(1) <= repeat; -- repeat
@@ -125,7 +132,7 @@ begin
else status_register when wslvi.adr(2) = '1'
else (others => '0');
interrupt <= '1' when counter = COUNT_MAX else '0';
interrupt <= '1' when counter = counter_target_value else '0';
wslvo.ack <= ack;
wslvo.wbcfg <= wb_membar(memaddr, addrmask);

7
soc/testbench/timer_tb.vhd
View File

@@ -86,11 +86,16 @@ BEGIN
wait for CLK_PERIOD*20;
-- Change target value
data <= std_logic_vector(to_unsigned(1024, data'length));
generate_sync_wb_single_write(slvi,slvo,clk,data);
-- Read status register
data <= (others => '0');
generate_sync_wb_single_read(slvi,slvo,clk,data, ADR_OFFSET => 4);
wait for CLK_PERIOD * 2;
wait until interrupt = '1';
wait for CLK_PERIOD * 5;
assert false report "Simulation terminated!" severity failure;
wait;