102 lines
1.7 KiB
Plaintext
102 lines
1.7 KiB
Plaintext
reset:
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br always >main
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nop
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hardfault:
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reti
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nop
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memfault:
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reti
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nop
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timer_interrupt:
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br >timer_interrupt_handler
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nop
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.align
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led_addr: .word 0x000F0000
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timer_counter_addr: .word 0x000F0008
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timer_status_addr: .word 0x000F000C
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dmem_start_addr: .word 0x00000400
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dmem_end_addr: .word 0x000004FC
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priority_mask: .word 0xFFFFFF03
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timer_target_value: .word 127 // change for simulation / real board
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main:
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// Initialize stack pointer to the end of the data memory
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ldr r12, >dmem_end_addr
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// Set runtime priority
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ldr r0, >priority_mask
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and r14, r0, r14
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ldr r0,>led_addr // LED addr
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ldr r1,>timer_status_addr // Timer addr
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ldr r3,>timer_counter_addr // Timer addr
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// Init
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clr r9 // 0 if we are currently filling, 1 if we are currently flushing
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clr r8 // shift register
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clr r5 // shift counter
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clr r4 // shift counter top constant
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addi r4, 10
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// Enable the timer...
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ldr r2, >timer_target_value // target value
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st32 r3, r2
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clr r2
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addi r2, 0x3 // enable and repeat bit set
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st32 r1, r2
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loop:
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br >loop
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nop
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timer_interrupt_handler:
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clr r10
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addi r10, 1
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cmp eq r9, r10
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br true >flush
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nop
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br always >fill
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nop
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rst_fill:
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clr r5
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fill:
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clr r9
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// When shift register full, jump to flush
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addi r5, 1
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cmp eq r5, r4
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br true >rst_flush
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nop
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lsh r8, r8, 1
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addi r8, 1
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st08 r0, r8
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reti
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nop
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rst_flush:
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clr r5
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flush:
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clr r9
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addi r9, 1
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// When shift register empty, jump to fill
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addi r5, 1
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cmp eq r5, r4
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br true >rst_fill
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nop
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lsh r8, r8, 1
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st08 r0, r8
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reti
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nop
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