lt16lab/soc/testbench/segment_tb.vhd

-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;
USE work.wishbone.ALL;
USE work.wb_tp.ALL;
USE work.config.ALL;

ENTITY segment_tb IS
END ENTITY;

ARCHITECTURE sim OF segment_tb IS

	constant CLK_PERIOD : time := 10 ns;

	signal clk 	: std_logic := '0';
	signal rst	: std_logic;
	
    signal seg_data : std_logic_vector(3 downto 0) := (others => '0');
    signal seg_off : std_logic := '0';
    signal seg_shift : std_logic := '0';
    signal seg_write : std_logic := '0';
    signal seg_clear : std_logic := '0';   
	
    signal anodes : std_logic_vector(7 downto 0);
    signal cathodes : std_logic_vector(7 downto 0);

    component seven_segment_display is
		port(
            clk		: in  std_logic;
            rst		: in  std_logic;
            seg_data : in std_logic_vector(3 downto 0);
            seg_off : in std_logic;
            seg_shift : in std_logic;
            seg_write : in std_logic;
            seg_clear : in std_logic;   
            anodes : out std_logic_vector(7 downto 0);
            cathodes : out std_logic_vector(7 downto 0)
		);
	end component;

BEGIN

	SIM_SLV: seven_segment_display
		port map(
			clk		=> clk,
			rst		=> rst,
            seg_data => seg_data,
            seg_off => seg_off,
            seg_shift => seg_shift,
            seg_write => seg_write,
            seg_clear => seg_clear,

            anodes => anodes,
            cathodes => cathodes
		);

	clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD/2;
	end process clk_gen;

	stimuli: process
	begin
		rst	<= '1';
		wait for CLK_PERIOD;
		rst	<= '0';

        seg_shift <= '0'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"F"; -- data

		wait for 1 us;
		
        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '0'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"0"; -- data
        
        wait for CLK_PERIOD;
        seg_shift <= '0';
		
        wait for 1 us;
        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"A"; -- data
        
        wait for CLK_PERIOD;
        seg_shift <= '0';
        
        wait for 1 us;
        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"B"; -- data

        wait for CLK_PERIOD;
        seg_shift <= '0';
        
        wait for 1 us;
        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"C"; -- 
        
        wait for CLK_PERIOD;
        seg_shift <= '0';        
        
        wait for 1 us;
        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '1'; -- off
        seg_data <= x"0"; -- data
        
        wait for CLK_PERIOD;
        seg_shift <= '0';        
        
        wait for 1 us;
        seg_shift <= '0'; -- shift
        seg_clear <= '1'; -- clear
        seg_write <= '0'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"0"; -- data
		
		wait for 1 us;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"D"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"E"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"A"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"D"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"B"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"E"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"E"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '1'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '1'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"F"; -- data
        wait for CLK_PERIOD;

        seg_shift <= '0'; -- shift
        seg_clear <= '0'; -- clear
        seg_write <= '0'; -- write
        seg_off <= '0'; -- off
        seg_data <= x"F"; -- data

        wait for 1 us;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;