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Some generic bug fixes

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This commit is contained in:
Derek Christ
2022-11-14 15:28:05 +01:00
parent 15f51c1793
commit acd1679ef9
8 changed files with 191 additions and 49 deletions
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120
programs/assignment2isr_.prog Executable file
View File

@@ -0,0 +1,120 @@
reset:
br always >main
nop
hardfault:
reti
nop
memfault:
reti
nop
irq3:
br always >irq3_handler
nop
.align
addr:
.word 0x000F0000
addrsw:
.word 0x000F0006
//w_cnt_top: .word 0x1FC000
w_cnt_top: .word 0x1 //for simulation only
// Constant Declaration
.align
sp_init: .word 0x400 // Stackpointer Initial Value
main:
ldr r12, >sp_init
clr r14
ldr r0,>addr //LED addr
ldr r2,>addrsw //sw addr
addi r6,8 //outer counter top
clr r7 //wait counter
here:
nop
nop
nop
br always >here
nop
out_loop:
ldr r8,>w_cnt_top
clr r1
st08 r0,r1
call >wait
nop
fill:
lsh r1,r1,1
addi r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >fill
nop
clr r5
flush:
lsh r1,r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >flush
nop
clr r5
br always >out_loop
nop
//subroutine to iterate until counter overflow
wait:
clr r3
ld16 r3,r2 //loading switches content to r3 from r2 address
clr r9
clr r10
clr r11
br always >nfound
nop
found: rsh r8,r8,1 //one found
nfound: clr r4
addi r4,1
addi r10,1 //loop counter max 16
and r9,r3,r4
cmp eq r9,r4
br true >found
rsh r3,r3,1
clr r4
addi r4,16
cmp le r10,r4
br true >nfound
nop
clr r7 //inititalize inner counter
inc_i:
cmp neq r7,r8
br true >inc_i //if i=cnt_top
addi r7,1
ret //else
nop
irq3_handler:
br always >out_loop
nop
reti

23
programs/segments_adv_test.prog
View File

@@ -10,8 +10,9 @@ nop
.align
segment_addr: .word 0x000F00A0
// w_cnt_top: .word 0xFFC000
w_cnt_top: .word 0x100 //for simulation only
w_cnt_top: .word 0xFFC000
// w_cnt_top: .word 0x100 //for simulation only
write_and_shift:
.word 0x01000100
@@ -112,7 +113,7 @@ number_loop:
// 0xDEADBEEF pattern:
clr r4
addi r4, 0xD
addi r4, 0xF
or r4, r4, r1
st32 r0, r4
@@ -122,12 +123,7 @@ number_loop:
st32 r0, r4
clr r4
addi r4, 0xA
or r4, r4, r1
st32 r0, r4
clr r4
addi r4, 0xD
addi r4, 0xE
or r4, r4, r1
st32 r0, r4
@@ -137,7 +133,12 @@ number_loop:
st32 r0, r4
clr r4
addi r4, 0xE
addi r4, 0xD
or r4, r4, r1
st32 r0, r4
clr r4
addi r4, 0xA
or r4, r4, r1
st32 r0, r4
@@ -147,7 +148,7 @@ number_loop:
st32 r0, r4
clr r4
addi r4, 0xF
addi r4, 0xD
or r4, r4, r1
st32 r0, r4

17
programs/segments_test.prog
View File

@@ -9,6 +9,8 @@ reti
nop
.align
led_addr: .word 0x000F0000
number_array0:
.word 0x03020100
number_array1:
@@ -20,17 +22,24 @@ number_array3:
segment_addr0: .word 0x000F00A0
segment_addr1: .word 0x000F00A4
// w_cnt_top: .word 0xFFC000
w_cnt_top: .word 0x100 //for simulation only
random_value: .word 0xAA
w_cnt_top: .word 0xFFFFFF // for real board
// w_cnt_top: .word 0x100 //for simulation only
infamous_pattern0:
.word 0x0D0E0A0D
.word 0x0F0E0E0B
infamous_pattern1:
.word 0x0B0E0E0F
.word 0x0D0A0E0D
main:
ldr r8, >w_cnt_top
ldr r0, >led_addr
// Set LEDs to some value
ldr r4, >random_value
st08 r0, r4
number_loop:
// First 4

12
programs/timer_blinky.prog
View File

@@ -22,7 +22,9 @@ dmem_start_addr: .word 0x00000400
dmem_end_addr: .word 0x000004FC
priority_mask: .word 0xFFFFFF03
// timer_target_value: .word 127 // for simulation
timer_target_value: .word 65536 // for real board
timer_target_value: .word 0xF10000 // for real board
random_value: .word 0xFF
random_value2: .word 0xAA
main:
// Initialize stack pointer to the end of the data memory
@@ -51,11 +53,19 @@ main:
addi r2, 0x3 // enable and repeat bit set
st32 r1, r2
// Set LEDs to some value
ldr r4, >random_value
st08 r0, r4
loop:
br >loop
nop
timer_interrupt_handler:
// Set LEDs to some value too see if handler is triggered
ldr r4, >random_value2
st08 r0, r4
clr r10
addi r10, 1
cmp eq r9, r10

34
soc/peripheral/hex2physical.vhd
View File

@@ -19,23 +19,23 @@ begin
process(hex)
begin
case hex is
when "10000" => cathodes <= "10000001"; -- "0"
when "10001" => cathodes <= "11110011"; -- "1"
when "10010" => cathodes <= "01001001"; -- "2"
when "10011" => cathodes <= "01100001"; -- "3"
when "10100" => cathodes <= "00110011"; -- "4"
when "10101" => cathodes <= "00100101"; -- "5"
when "10110" => cathodes <= "00000101"; -- "6"
when "10111" => cathodes <= "11110001"; -- "7"
when "11000" => cathodes <= "00000001"; -- "8"
when "11001" => cathodes <= "00100001"; -- "9"
when "11010" => cathodes <= "00010001"; -- "A"
when "11011" => cathodes <= "00000111"; -- "B"
when "11100" => cathodes <= "10001101"; -- "C"
when "11101" => cathodes <= "01000011"; -- "D"
when "11110" => cathodes <= "00001101"; -- "E"
when "11111" => cathodes <= "00011101"; -- "F"
when others => cathodes <= "11111111"; -- "Off"
when "10000" => cathodes <= not "11111100"; -- "0"
when "10001" => cathodes <= not "01100000"; -- "1"
when "10010" => cathodes <= not "11011010"; -- "2"
when "10011" => cathodes <= not "11110010"; -- "3"
when "10100" => cathodes <= not "01100110"; -- "4"
when "10101" => cathodes <= not "10110110"; -- "5"
when "10110" => cathodes <= not "10111110"; -- "6"
when "10111" => cathodes <= not "11100000"; -- "7"
when "11000" => cathodes <= not "11111110"; -- "8"
when "11001" => cathodes <= not "11110110"; -- "9"
when "11010" => cathodes <= not "11101110"; -- "A"
when "11011" => cathodes <= not "00111110"; -- "B"
when "11100" => cathodes <= not "10011100"; -- "C"
when "11101" => cathodes <= not "01111010"; -- "D"
when "11110" => cathodes <= not "10011110"; -- "E"
when "11111" => cathodes <= not "10001110"; -- "F"
when others => cathodes <= not "00000000"; -- "Off"
end case;
end process;

9
soc/peripheral/seven_segment_display.vhd
View File

@@ -62,7 +62,8 @@ begin
);
timer: simple_timer
generic map (timer_start => x"00000008")
generic map (timer_start => x"00000008") -- for simulation
-- generic map (timer_start => x"00000F00") -- for board
port map(
clk => clk,
rst => rst,
@@ -108,7 +109,7 @@ begin
if clk'event and clk='1' then
if rst = '1' then
hex <= hex_register(4 downto 0);
anodes <= (others => '0');
anodes <= (others => not '0');
overflow_counter <= 0;
else
if timer_overflow = '1' then
@@ -118,8 +119,8 @@ begin
overflow_counter <= overflow_counter + 1;
end if;
anodes <= (others => '0');
anodes(overflow_counter) <= '1';
anodes <= (others => not '0');
anodes(overflow_counter) <= not '1';
hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
end if;

9
soc/peripheral/seven_segment_display_adv.vhd
View File

@@ -64,7 +64,8 @@ begin
);
timer: simple_timer
generic map (timer_start => x"00000008")
-- generic map (timer_start => x"00000008") -- for simulation
generic map (timer_start => x"00000F00") -- for board
port map(
clk => clk,
rst => rst,
@@ -149,7 +150,7 @@ begin
if clk'event and clk='1' then
if rst = '1' then
hex <= hex_register(4 downto 0);
anodes <= (others => '0');
anodes <= (others => not '0');
overflow_counter <= 0;
else
if timer_overflow = '1' then
@@ -159,8 +160,8 @@ begin
overflow_counter <= overflow_counter + 1;
end if;
anodes <= (others => '0');
anodes(overflow_counter) <= '1';
anodes <= (others => not '0');
anodes(overflow_counter) <= not '1';
hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
end if;

16
soc/top/top.xdc
View File

@@ -53,14 +53,14 @@ set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7]
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { cathodes[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cathodes[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cathodes[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cathodes[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { cathodes[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cathodes[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cathodes[6] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { cathodes[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { cathodes[7] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cathodes[6] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cathodes[5] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cathodes[4] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { cathodes[3] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cathodes[2] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cathodes[1] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { cathodes[0] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { anodes[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { anodes[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { anodes[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]