Add testbench that tests the switches prescaling

programs/assignment2code.prog

@@ -1,64 +1,86 @@
 reset:
-br always >main
-nop
+    br always >main
+    nop
 hardfault:
-reti
-nop
+    reti
+    nop
 memfault:
-reti
-nop
+    reti
+    nop
 
 .align
-addr:
-.word 0x000F0000
-//w_cnt_top:	.word 0x1FC000
-w_cnt_top:	.word 0x1		//for simulation only
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+base_prescaler: .word 0x1
 
 main:
-ldr r0,>addr	//LED addr
-addi r6,8		//outer counter top
-clr r7			//wait counter
-ldr r8,>w_cnt_top
+    ldr r0,>led_addr    //LED addr
+    addi r6,8        //outer counter top
+    clr r7            //wait counter
+    ldr r8,>base_prescaler
 
 out_loop:
-clr r1
-st08 r0,r1
-call >wait
-nop
+    clr r1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
 
 fill:
-	lsh r1,r1,1
-	addi r1,1
-	st08 r0,r1
-	call >wait
-	nop
+    lsh r1,r1,1
+    addi r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
 
-	addi r5,1
-	cmp neq r5,r6
-	br true >fill
-	nop
-	clr r5
+    addi r5,1
+    cmp neq r5,r6
+    br true >fill
+    nop
+    clr r5
 
 flush:
-	lsh r1,r1,1
-	st08 r0,r1
-	call >wait
-	nop
+    lsh r1,r1,1
+    st08 r0,r1
+    call >wait_prescaled
+    nop
+
+    addi r5,1
+    cmp neq r5,r6
+    br true >flush
+    nop
+    clr r5
+    br always >out_loop
+    nop
+
+wait_prescaled:
+    // Load value from the switches
+    ldr r11,  >switches_addr
+    ld32 r9, r11
+    addi r9, 1
+
+    clr r11
+    add r11, r13, r11 // save link register
+
+    clr r10
+inc_j:
+    call >wait
+    cmp neq r10,r9
+    br true >inc_j
+    addi r10,1
+
+    clr r13
+    add r13, r13, r11 // restore link register
+
+    ret
+    nop
 
-	addi r5,1
-	cmp neq r5,r6
-	br true >flush
-	nop
-	clr r5
-	br always >out_loop
-	nop
 
 //subroutine to iterate until counter overflow
 wait:
-	clr r7				//inititalize inner counter
-	inc_i:
-	cmp neq r7,r8
-	br true >inc_i		//if i=cnt_top
-	addi r7,1
-	ret					//else
-	nop
+    clr r7                //inititalize inner counter
+inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

soc/testbench/warmup2.vhd

@@ -0,0 +1,65 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup2_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup2_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0);
+    signal sw : std_logic_vector(15 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/assignment2code.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		btn <= (others => '0');
+		sw <= (others => '0');
+		wait for 2000*CLK_PERIOD;
+		sw(2) <= '1';
+		wait for 2000*CLK_PERIOD;
+        btn <= (others => '1');
+		wait for 2000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;