118 lines
3.3 KiB
VHDL
118 lines
3.3 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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entity seven_segment_display is
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port(
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clk : in std_logic;
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rst : in std_logic;
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seg_data : in std_logic_vector(3 downto 0);
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seg_off : in std_logic;
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seg_shift : in std_logic;
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seg_write : in std_logic;
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seg_clear : in std_logic;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end seven_segment_display;
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architecture Behavioral of seven_segment_display is
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signal hex_register : std_logic_vector(63 downto 0);
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signal hex : std_logic_vector(4 downto 0);
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signal timer_overflow : std_logic;
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signal overflow_counter : integer range 0 to 7;
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component hex2physical
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port(
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hex : in std_logic_vector(4 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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component simple_timer
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generic(
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timer_start : std_logic_vector (31 downto 0)
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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timer_overflow : out std_logic
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);
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end component;
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begin
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converter : hex2physical
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port map(
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hex => hex,
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cathodes => cathodes
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);
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timer: simple_timer
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generic map (timer_start => x"00000008") -- for simulation
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-- generic map (timer_start => x"00000F00") -- for board
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port map(
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clk => clk,
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rst => rst,
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timer_overflow => timer_overflow
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);
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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hex_register <= (others=>'0');
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else
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-- No special care has to be taken to support
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-- writing and shifting at the same time.
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if seg_shift = '1' then
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hex_register(63 downto 56) <= (others => '0');
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hex_register(55 downto 0) <= hex_register(63 downto 8);
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end if;
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if seg_write = '1' then
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hex_register(59 downto 56) <= seg_data;
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hex_register(60) <= not seg_off; -- unclear if this should only be set when write is 1
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end if;
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if seg_clear = '1' then
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hex_register <= (others => '0');
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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hex <= hex_register(4 downto 0);
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anodes <= (others => not '0');
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overflow_counter <= 0;
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else
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if seg_clear = '1' then
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overflow_counter <= 0;
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elsif timer_overflow = '1' then
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if overflow_counter = 7 then
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overflow_counter <= 0;
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else
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overflow_counter <= overflow_counter + 1;
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end if;
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anodes <= (others => not '0');
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anodes(overflow_counter) <= not '1';
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hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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