59 lines
1.1 KiB
VHDL
59 lines
1.1 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY work;
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USE work.lt16soc_peripherals.ALL;
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ENTITY simple_timer_tb IS
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END ENTITY;
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ARCHITECTURE sim OF simple_timer_tb IS
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic;
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signal clk : std_logic := '0';
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signal overflow : std_logic;
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component simple_timer
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generic(
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timer_start : std_logic_vector (31 downto 0)
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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timer_overflow : out std_logic
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);
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end component;
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BEGIN
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timer: simple_timer
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generic map (timer_start => x"0000001F")
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port map(
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clk => clk,
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rst => rst,
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timer_overflow => overflow
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '1';
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wait for CLK_PERIOD;
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rst <= '0';
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wait for 5 us;
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assert false report "Simulation terminated!" severity failure;
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end process stimuli;
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END ARCHITECTURE;
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