-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;

ENTITY simple_timer_tb IS
END ENTITY;

ARCHITECTURE sim OF simple_timer_tb IS

    constant CLK_PERIOD : time := 10 ns;

    signal rst : std_logic;
    signal clk : std_logic := '0';
	signal overflow : std_logic;

    component simple_timer
        generic(
            timer_start : std_logic_vector (31 downto 0)
        );
        port(
            clk : in std_logic;
            rst : in std_logic;
            timer_overflow : out std_logic
        );
    end component;

BEGIN

	timer: simple_timer
        generic map (timer_start => x"0000001F")
        port map(
			clk => clk,
            rst => rst,
            timer_overflow => overflow
    );

    clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD/2;
	end process clk_gen;

	stimuli: process
	begin
        rst <= '1';
        wait for CLK_PERIOD;
        rst <= '0';

		wait for 5 us;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;