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• 8479a691aa stdlib,python: Allow setting of to tick exits via m5 Bobby R. Bruce 2022-11-30 15:02:05 -08:00
• eee42275ee dev-amdgpu: Writeback RLC queue MQD when unmapped Matthew Poremba 2022-11-18 16:47:50 -08:00
• c0d67cba3a systemc: fix extension not found TlmToGem5 bridge response path Yu-hsin Wang 2022-11-23 11:00:23 +08:00
• d89d77f1c2 fastmodel: correct the Iris namespace for FastModel 11.19 Yu-hsin Wang 2022-10-12 11:20:44 +08:00
• aeb617868f stdlib: Add MESI Three Level cache hierarchy Hoa Nguyen 2022-11-14 03:13:35 +00:00
• eac06ad681 python: Fix multiline quotes in a single line Hoa Nguyen 2022-11-28 03:26:32 +00:00
• f99947059d stdlib: Clean up Ruby cache directory Hoa Nguyen 2022-11-12 08:00:49 +00:00
• c8949f085f stdlib: Change #virtual_networks of mesi_two_level to 3 Hoa Nguyen 2022-11-14 03:36:52 +00:00
• 8391f47bc9 stdlib: More helpful message for the filelock error Hoa Nguyen 2022-11-26 00:48:18 +00:00
• 770b84c2ee sim: Add missing virtual destructor to GlobalSyncEvent Bobby R. Bruce 2022-11-28 13:02:49 -08:00
• ea3f13ff3b configs: Set CPU vendor to M5 Simulator in apu_se.py Matthew Poremba 2022-11-23 14:20:14 -08:00
• 92027a68ce configs: Set CPU vendor to M5 Simulator in apu_se.py Matthew Poremba 2022-11-23 14:20:14 -08:00
• ee9e07474b tests: Delete build directory before running KVM in nightly Bobby R. Bruce 2022-11-22 14:30:35 -08:00
• d51ce0db94 configs: Add missing _pre_instantiate call in "run_lupv.py" Bobby R. Bruce 2022-11-21 13:25:57 -08:00
• 753470e8fa tests: Update riscvmatched tests to use ALL/gem5.opt Bobby R. Bruce 2022-11-21 12:05:29 -08:00
• 793076f2bd configs,stdlib,tests: Update riscvmatched-fs.py to-init Bobby R. Bruce 2022-11-21 11:57:40 -08:00
• 373b8658f4 configs,stdlib: Fix import in riscvmatched-fs.py Bobby R. Bruce 2022-11-21 11:56:23 -08:00
• f34f582dcf stdlib,configs: Update riscvmatched-fs example docstring Bobby R. Bruce 2022-11-21 11:52:57 -08:00
• 9696cb517a arch-arm: Revert 'Setup TC/ISA at construction time..' Bobby R. Bruce 2022-11-17 15:48:34 -08:00
• 98f3d779b7 arch-x86: X86ISA default vector_string to HygonGenuine Bobby R. Bruce 2022-11-10 17:07:11 -08:00
• 4054565b85 tests: Delete build directory before running KVM in nightly Bobby R. Bruce 2022-11-22 14:30:35 -08:00
• d401b1fbad base,sim: Adding monitor function to GDB Quentin Forcioli 2022-08-16 17:43:31 +02:00
• 7230a3e7f0 base,sim,ext: Adding GDB signals definition Quentin Forcioli 2022-08-18 12:26:12 +02:00
• da12e96507 configs: Add missing _pre_instantiate call in "run_lupv.py" Bobby R. Bruce 2022-11-21 13:25:57 -08:00
• db35dfb942 tests: Update riscvmatched tests to use ALL/gem5.opt Bobby R. Bruce 2022-11-21 12:05:29 -08:00
• 5794643e44 configs,stdlib,tests: Update riscvmatched-fs.py to-init Bobby R. Bruce 2022-11-21 11:57:40 -08:00
• 36f2964d19 configs,stdlib: Fix import in riscvmatched-fs.py Bobby R. Bruce 2022-11-21 11:56:23 -08:00
• 00c2f09bd9 stdlib,configs: Update riscvmatched-fs example docstring Bobby R. Bruce 2022-11-21 11:52:57 -08:00
• d7b3020324 dev,mem,systemc: Implement and use the recvMemBackdoorReq func. Gabe Black 2022-10-01 03:18:20 -07:00
• 842a3a935f mem: Add an API for requesting a back door without a Packet/Request. Gabe Black 2022-09-27 02:56:10 -07:00
• ff16ca3daf mem: Add a class to describe a back door request. Gabe Black 2022-09-27 02:52:42 -07:00
• 5eb73551bd fastmodel: CortexR52 export standbywfi signal Yu-hsin Wang 2022-11-14 16:11:57 +08:00
• ec75787aef arch-arm: Revert 'Setup TC/ISA at construction time..' Bobby R. Bruce 2022-11-17 15:48:34 -08:00
• 33a36d35de dev-amdgpu: Store SDMA queue type, use for ring ID Matthew Poremba 2022-11-17 08:54:43 -08:00
• 6651329cc5 base: query now works the same way normal command worked Quentin Forcioli 2022-08-25 14:52:09 +02:00
• a49cba9480 arch-x86: X86ISA default vector_string to HygonGenuine Bobby R. Bruce 2022-11-10 17:07:11 -08:00
• dff879cf21 configs, gpu-compute: Add configurable L1 scalar latencies vramadas95 2022-11-10 20:42:25 -06:00
• 04767ddc62 dev-amdgpu: Fix SDMA ring buffer wrap around Matthew Poremba 2022-11-07 16:28:15 -08:00
• 729a9399e4 arch-vega: Fix SOPK instruction sign extends Matthew Poremba 2022-11-08 19:58:07 -08:00
• 56c359c41b dev-amdgpu: Handle ring buffer wrap for PM4 queue Matthew Poremba 2022-11-08 14:24:32 -08:00
• f172c41c68 stdlib: Fix get_isa_from_str() exception behavior in isas.py Jasjeet Rangi 2022-11-07 15:09:24 -08:00
• 78b978686c stdlib: Fix get_isa_from_str() exception behavior in isas.py Jasjeet Rangi 2022-11-07 15:09:24 -08:00
• 8693d725e2 arch-vega: Fix SOPK instruction sign extends Matthew Poremba 2022-11-08 19:58:07 -08:00
• 623e2d3dac dev-amdgpu: Handle ring buffer wrap for PM4 queue Matthew Poremba 2022-11-08 14:24:32 -08:00
• 90046bae6f systemc: Add the stream id entry and its conversion in control extension handsomeliu 2022-11-08 15:39:28 +08:00
• c8d687b05c dev-amdgpu: Fix SDMA ring buffer wrap around Matthew Poremba 2022-11-07 16:28:15 -08:00
• 8d63c9fc06 gpu-compute: Add granulated SGPR computation for gfx9 Matthew Poremba 2022-11-02 14:58:29 -07:00
• f6dc5c6aa4 gpu-compute: Chunkify AMDKernelCode read from device Matthew Poremba 2022-11-02 14:57:51 -07:00
• 553096ee53 stdlib: Make the Matched board a package Hoa Nguyen 2022-11-07 16:25:15 -08:00
• 5d0a7b6a6c arch-riscv: Updating the SD bit of mstatus upon the register read Hoa Nguyen 2022-11-03 16:42:53 -07:00
• dd2f1fb2f8 arch-arm: Setup ISA::gicv3CpuInterface on demand only Giacomo Travaglini 2022-10-24 09:49:44 +01:00
• 47bd56ee71 dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface Giacomo Travaglini 2022-11-04 14:48:31 +00:00
• a4f86df266 arch-riscv: Update FS field of mstatus register where approriate. Hoa Nguyen 2022-11-03 16:11:46 -07:00
• 3b8125d28e arch-riscv: Add VS field to the STATUS CSR Hoa Nguyen 2022-11-03 17:30:16 -07:00
• 26c27b1bf8 stdlib: Change the default kernel boot param from "ro" to "rw" Hoa Nguyen 2022-11-01 13:48:12 -07:00
• c871d25ede stdlib: Fixing erroneous typing in Simulator __init__ Bobby R. Bruce 2022-10-18 15:20:55 -07:00
• 353c20e8bf stdlib: Fix typos and remove unneeded import in Simulator Bobby R. Bruce 2022-08-30 15:52:47 -07:00
• c88b528738 stdlib: Update AbstractCore's 'set_inst_stop_any_thread' Bobby R. Bruce 2022-10-19 14:12:44 -07:00
• 12d8d5ca26 stdlib: Update AbstractCore set_simpoint func Bobby R. Bruce 2022-10-19 13:34:39 -07:00
• 905b71c375 python: Move find from group to AbstractStat Bobby R. Bruce 2022-09-16 10:51:44 -07:00
• b65fa9e0d8 python: Add AbstractStat for PyStats Bobby R. Bruce 2022-09-15 13:40:49 -07:00
• 68f8c2946d stdlib: Add 'get_simstats' function to simulator Bobby R. Bruce 2022-09-07 12:34:17 -07:00
• 4a06375212 stdlib: Add __repr__ to pystats Bobby R. Bruce 2022-09-07 12:31:18 -07:00
• be33be87da misc: Update black to process src/python/m5/ext/pystats Bobby R. Bruce 2022-09-16 13:01:57 -07:00
• 5204b58e19 stdlib: Rename JsonSerializable to SerializableStat Bobby R. Bruce 2022-04-29 18:08:03 -07:00
• 2211fdb607 tests,stdlib: Add a test for JsonSerializable Bobby R. Bruce 2022-04-08 17:04:24 -07:00
• 23d405ea55 tests, resources: CVE-2007-4559 Patch Melissa Jost 2022-11-03 09:06:03 -07:00
• f61a640d30 mem: Fix SHM server path cleanup logic Jui-Min Lee 2022-11-02 13:38:12 +08:00
• 5bf88bf7a1 sim: allow specifying remote gdb port for each workload Earl Ou 2022-10-31 22:36:29 -07:00
• 540e6515de ext: upgrade to googletest 1.12.0 Yu-hsin Wang 2022-11-02 16:26:05 +08:00
• c6918c8f74 python,stdlib: Add multiprocessing module Jason Lowe-Power 2022-09-09 13:01:51 -07:00
• aead8fb0fd arch-arm: Remove ISA::haveGICv3CpuIfc method Giacomo Travaglini 2022-10-27 14:00:25 +01:00
• d348df8763 arch-arm: Fix GICv3 List register mapping Giacomo Travaglini 2022-10-31 14:25:19 +00:00
• ba8f59ff17 arch-arm: Fix access permissions for GICv3 cpu registers Giacomo Travaglini 2022-10-31 13:58:14 +00:00
• e65adccd6f util: update termios to replace nl with cr-nl Earl Ou 2022-11-01 01:00:57 -07:00
• 19bad67a6e tests: Remove ARM compilation requirement for quick/Kokoro Bobby R. Bruce 2022-11-01 13:57:46 -07:00
• 54322872dd tests: Remove unneeded build step from nightly.sh Bobby R. Bruce 2022-11-01 13:12:41 -07:00
• 3c171a1ae4 tests: Remove tests requiring comp of novel ISAs in long Bobby R. Bruce 2022-11-01 13:03:35 -07:00
• e07ca68ed7 tests: Remove long/nightly X86 Boot tests Bobby R. Bruce 2022-11-01 12:29:59 -07:00
• 4145d9fb91 tests: Remove long/nightly ARM Boot tests Bobby R. Bruce 2022-11-01 12:19:22 -07:00
• 8ffecdd966 stdlib,configs,tests: Rename config to arm-ubuntu-run.py Bobby R. Bruce 2022-10-31 12:00:40 -07:00
• 26858db854 stdlib: Refactor the ArmBoard for _connect_things move Bobby R. Bruce 2022-10-27 15:28:28 -07:00
• 25d4fb2d91 stdlib: Move _connect_things to run as pre_instantiation Bobby R. Bruce 2022-10-27 15:16:58 -07:00
• 75c1df0d06 stdlib,arch-arm: Add ruby cache support to the ArmBoard Kaustav Goswami 2022-09-29 17:30:50 -07:00
• 04ac9d9f4f stdlib: Give board interface for mem ports Jason Lowe-Power 2022-10-14 10:06:07 -07:00
• 27da9b3576 configs: GPUFS: use multiple event queues for >1 CPU Matthew Poremba 2022-10-30 11:47:01 -07:00
• 489074fbfd dev-amdgpu: Fix issues with PM4 queue map, fences Matthew Poremba 2022-10-30 12:41:47 -07:00
• c5feca8251 dev-amdgpu: Rework PM4 NOP packet Matthew Poremba 2022-10-30 12:23:48 -07:00
• 752b696883 dev-amdgpu: Fix SDMA trap ring ID, context Matthew Poremba 2022-10-30 12:12:49 -07:00
• 8899291db6 dev-amdgpu: Fix interrupt handler address assignment Matthew Poremba 2022-10-30 12:00:04 -07:00
• 91cd599f05 systemc: sync the response error between gem5 packet and tlm payload Yu-hsin Wang 2022-10-12 10:39:57 +08:00
• 80c3bd3bdf mem: introduce bad command error to packet commands Yu-hsin Wang 2022-10-21 11:53:12 +08:00
• 144ce7f12c dev-amdgpu: Fix GART PTE size Matthew Poremba 2022-10-30 11:48:56 -07:00
• 7b16b17e61 dev-amdgpu: Chunkify SDMA copies that use device memory Matthew Poremba 2022-10-18 13:01:33 -07:00
• 6a4a12ebbd arch-vega: Improve non-native page size support Matthew Poremba 2022-10-18 12:56:48 -07:00
• 6fd2a64656 mem: implement ThreadBridge Earl Ou 2022-10-27 22:40:00 -07:00
• 3ab6a7496b stdlib: Move setting of checkpoints to set_workload funcs Bobby R. Bruce 2022-10-12 18:40:45 -07:00
• ceac4b8f1a stdlib,configs: Update simpoint example to use the Workload Melissa Jost 2022-10-06 10:02:24 -07:00
• 36e5feb0de stdlib: add 'get_simpoint' function to se_binary_workload.py Bobby R. Bruce 2022-10-13 14:24:06 -07:00
• f1be0c808a stdlib: Added set_se_simpoint_workload to SEBinaryWorkload Melissa Jost 2022-10-12 14:28:17 -07:00