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• 717d3b239c base,python: Added PcCountPair type and parameter Zhantong Qiu 2023-01-06 16:11:57 -08:00
• e1601954f0 stdlib: Implement Simpoint Resources Bobby R. Bruce 2023-01-20 13:40:22 +00:00
• cc838d72a6 stdlib: Update resources to have downloads optional Bobby R. Bruce 2023-01-20 00:34:09 +00:00
• a9b69ee055 stdlib: Add null/None versioning in resources.json Bobby R. Bruce 2023-01-19 14:30:19 +00:00
• 4ee724e054 stdlib: Specialize the gem5-resources Bobby R. Bruce 2023-01-06 16:58:16 +00:00
• 3892ee029a configs: Deprecate fs.py and se.py scripts Bobby R. Bruce 2023-02-19 23:49:28 +00:00
• c995d96956 arch-arm: Add missing <array> header in regs/misc.hh Ivan Turasov 2023-02-21 14:46:02 +01:00
• 4dfc312d6d base: extensible: add example codes of extension Yan Lee 2023-02-16 20:56:19 -08:00
• 4c9253761f mem: add extension mechanism into Request Yan Lee 2023-02-14 19:50:49 -08:00
• c913c098a6 mem: add extension mechanism into Packet Yan Lee 2023-02-14 19:50:10 -08:00
• df0bed6858 python: Ensure that m5.internal.params is available Nikos Nikoleris 2023-02-09 09:33:17 +00:00
• 109c327209 base: add extensible type Yan Lee 2023-02-14 19:47:38 -08:00
• f028bd55e0 arch-vega: Update API for some flat atomics Matthew Poremba 2023-02-15 07:45:57 -08:00
• 3b4f241fb5 arch-riscv: Fix incorrect trap value of instruction fault Roger Chang 2023-01-17 10:38:11 +08:00
• 4b1c245420 arch-riscv: Fix the behavior of write to status CSR Roger Chang 2023-02-14 10:26:09 +08:00
• e10be09dcf dev: add method to set initial register value out of constructor. hungweihsu 2023-02-09 05:39:15 +00:00
• ea9239ae09 dev-amdgpu: Update deprecated ports Matthew Poremba 2023-02-09 12:03:38 -06:00
• bb8f370e4d arch-vega: Implementing global_atomic_smax Alexandru Dutu 2022-10-07 17:33:50 -07:00
• 8375058e73 arch-vega: Implementing global_atomic_smin Alexandru Dutu 2022-10-07 17:22:12 -07:00
• d7516a26dc arch-vega: Implementing global_atomic_or Alexandru Dutu 2022-10-07 17:11:35 -07:00
• 39b5b5e511 dev-amdgpu: Fix address in POLL_REGMEM SDMA packet Matthew Poremba 2023-02-13 10:58:12 -06:00
• b6a591e203 mem-dram: Make sure SHOW_SIM_OUTPUT is in global namespace. Zhengrong Wang 2023-02-10 22:34:28 -08:00
• 39e813374c ext: Fix typo in DRAMSIM2 Sconscript Zhengrong Wang 2023-02-08 20:41:26 -08:00
• bc9e90d65e arch-vega: Make VGPR-offset for global SGPR-base signed Matthew Poremba 2023-01-03 11:40:45 -08:00
• 905b8ebd22 arch-vega: Implement ds_write_b8_d16_hi Matthew Poremba 2023-01-03 08:08:05 -08:00
• 89c49d1ab0 arch-riscv: Fix the CSR instruction behavior. zhongchengyong 2023-02-07 22:21:53 +08:00
• bd9e126d5e cpu: Add a generic model_reset port on the BaseCPU. Gabe Black 2023-02-02 04:59:26 -08:00
• d1f76741c6 dev: Add a definition for VectorResetResponsePort. Gabe Black 2023-02-02 07:50:12 -08:00
• aee282b79f tests: Update testing documentation Melissa Jost 2022-11-16 15:26:33 -08:00
• e44cbe724b sim: handle async events in main thread only Earl Ou 2023-02-01 21:55:51 -08:00
• 7371e46822 mem: use default backdoor behavior for thread_bridge Earl Ou 2023-02-01 21:54:05 -08:00
• 8a774e07b2 dev-amdgpu: Patch forgotten port after mem port owner deprecation Gabriel Busnot 2023-02-06 12:51:22 +00:00
• a513e06a1b fastmodel: Export the reset signals of the GIC. Gabe Black 2023-02-02 07:03:47 -08:00
• 59e16b5695 fastmodel: forward stream ID to gem5 Wei-Han Chen 2023-02-03 03:21:27 +00:00
• a2d321d475 fastmodel: change the constructor of bridges Wei-Han Chen 2023-01-17 02:52:52 +00:00
• c9719b44a3 arch-riscv: Implement the resetThread method on the ISA object. Gabe Black 2023-02-02 04:53:50 -08:00
• c853187273 arch: Add a virtual method to the BaseISA to reset its ThreadContext. Gabe Black 2023-02-02 04:50:19 -08:00
• de3dba971c arch-riscv: Get rid of redundant reset fault invocation. Gabe Black 2023-02-02 03:26:42 -08:00
• d7cb6ac2b1 base: Turn all logging.hh macros into expression kind Gabriel Busnot 2023-01-20 13:01:46 +00:00
• cd2f8b3e6f base: Enable non-copiable types in gem5_assert message formatting Gabriel Busnot 2023-01-20 09:37:30 +00:00
• a0f6f85ad1 sim: Suppress deleted operator= warn in Sys::Threads::const_it Gabriel Busnot 2023-01-24 10:02:17 +00:00
• 7f4c92c910 mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner Gabriel Busnot 2023-01-06 11:22:26 +00:00
• d40ed0f826 mem: Deprecate RequestPort and ResponsePort owner ref member Gabriel Busnot 2023-02-02 08:31:07 +00:00
• c1b1a702f9 tests: Make the GTestException type accessible to unit tests Gabriel Busnot 2023-01-25 07:28:39 +00:00
• 3bdbe482c2 base: Strengthen safe_cast and make it work for reference types Gabriel Busnot 2023-01-24 09:59:30 +00:00
• 1b949e9759 dev: terminal: run pollevent in terminal eventq Earl Ou 2023-02-01 21:55:05 -08:00
• f2562152e8 arch-riscv,sim-se: Support RV32 register ABI call Roger Chang 2022-11-15 13:48:53 +00:00
• e4be93b55f sim: Add some helpers for setting up Signal*Ports in python. Gabe Black 2023-01-31 09:38:02 -08:00
• 13dca0ebcb scons: Link tcmalloc_minimal by default instead of tcmalloc Gabriel Busnot 2023-01-18 15:22:11 +00:00
• a33b4931d7 mem-cache: schedule already ready pf next cycle Nathanael Premillieu 2023-01-27 15:11:19 +01:00
• d48e53e0a2 scons: force libasan to static linking Johnny 2023-01-18 13:43:49 +08:00
• 534d9dea10 scons: Raise bin size limit for sanitized builds. Gabriel Busnot 2023-01-24 08:28:48 +00:00
• 8d0fde1961 python: Fix deprecated decorator Gabriel Busnot 2023-01-19 11:08:51 +00:00
• 8110a42266 arch-arm: Replace Loader with loader namespace in SME code Giacomo Travaglini 2023-01-18 08:53:02 +00:00
• 5a1414d782 arch: Remove a couple of deprecated namespaces Daniel R. Carvalho 2023-01-14 10:16:09 -03:00
• 0bce2e56d9 dev: Ignore MC146818 UIP bit / Fix x86 Linux 5.11+ boot Matthew Poremba 2022-12-15 13:11:44 -08:00
• b860e2039b system-arm: Enable SME in the bootloader Sascha Bischoff 2022-08-03 17:21:48 +01:00
• c694d8589f arch-arm, cpu: Implement instructions added by FEAT_SME Sascha Bischoff 2022-08-03 17:10:29 +01:00
• fe8eda9c4e arch, arch-arm, cpu: Add matrix reg support to the ISA Parser Sascha Bischoff 2022-08-03 15:38:46 +01:00
• 142d562b2f arch-arm: Implement SME access traps and extend the SVE ones Sascha Bischoff 2022-08-03 14:57:33 +01:00
• 72e4f614a2 arch-arm: Add interfaces to set and get SME vector length Sascha Bischoff 2022-08-03 14:54:04 +01:00
• dfd151d52d arch-arm: Add system registers added/used by SME Sascha Bischoff 2022-08-03 13:40:02 +01:00
• 5c43523d53 arch-arm: Add matrix register support for SME Sascha Bischoff 2022-08-09 16:42:01 +01:00
• fed81f3408 arch,cpu: Add boilerplate support for matrix registers Sascha Bischoff 2022-08-09 09:37:47 +01:00
• dd6595bf56 mem-cache: masked writes are not whole-line writes Sascha Bischoff 2022-08-03 17:11:30 +01:00
• befa5baa78 cpu-o3: print VecPredReg not VecReg Sascha Bischoff 2022-08-31 10:37:02 +01:00
• 41b5276c1c cpu-o3: Remove obsolete getRegIds and getTrueId Sascha Bischoff 2022-08-09 10:47:28 +01:00
• 39bbd9c05e sim,arch: Remove the GuestABI namespace Daniel R. Carvalho 2023-01-14 10:13:31 -03:00
• 31a1d485af sim: Remove a couple of deprecated namespaces Daniel R. Carvalho 2023-01-14 10:07:43 -03:00
• c8e3708d89 sim: Remove the Enums namespace Daniel R. Carvalho 2023-01-14 10:11:21 -03:00
• c1c79615e0 sim: Remove the ProbePoints namespace Daniel R. Carvalho 2023-01-14 10:07:08 -03:00
• 5f5aae8940 dev: Remove a couple of deprecated namespaces Daniel R. Carvalho 2023-01-14 10:02:16 -03:00
• 161519177e cpu: Remove the Minor namespace Daniel R. Carvalho 2023-01-14 10:00:39 -03:00
• 2ec3f64af8 cpu: Remove the DecodeCache namespace Daniel R. Carvalho 2023-01-14 10:00:09 -03:00
• 93f0de95d6 misc: Remove the m5 namespace Daniel R. Carvalho 2023-01-14 09:57:55 -03:00
• 1e80ba7862 misc: Remove the Net namespace Daniel R. Carvalho 2023-01-14 09:56:59 -03:00
• b2bf811aea misc: Remove the FreeBSD namespace Daniel R. Carvalho 2023-01-14 09:56:06 -03:00
• d14cde6bd7 misc: Remove the Linux namespace Daniel R. Carvalho 2023-01-14 09:55:26 -03:00
• c1839aad77 fastmodel: Remove the FastModel namespace Daniel R. Carvalho 2023-01-14 09:52:45 -03:00
• cc3d75ad72 base: Remove the Loader namespace Daniel R. Carvalho 2023-01-14 09:59:03 -03:00
• 544d53798b base: Remove the Units namespace Daniel R. Carvalho 2023-01-14 09:53:34 -03:00
• d2bfb4aeef base: Remove the Debug namespace Daniel R. Carvalho 2023-01-14 09:58:30 -03:00
• 4f480fc6fc base: Remove the Stats namespace Daniel R. Carvalho 2023-01-14 09:51:32 -03:00
• 65317b6fc9 base: Remove the BloomFilter namespace Daniel R. Carvalho 2023-01-14 09:50:13 -03:00
• e881f2603c mem: Remove the ContextSwitchTaskId namespace Daniel R. Carvalho 2023-01-14 10:14:33 -03:00
• 813c27c97a mem: Remove the QoS namespace Daniel R. Carvalho 2023-01-14 09:59:35 -03:00
• 82aa4c8358 mem-cache: Remove the Encoder namespace Daniel R. Carvalho 2023-01-14 10:01:34 -03:00
• de408fbd4e mem-cache: Remove the Compressor namespace Daniel R. Carvalho 2023-01-14 09:48:54 -03:00
• 65c15ba188 mem-cache: Remove the Prefetcher namespace Daniel R. Carvalho 2023-01-14 09:41:36 -03:00
• d4c1904ce6 mem-cache: Remove the ReplacementPolicy namespace Daniel R. Carvalho 2023-01-14 09:35:26 -03:00
• 6e74deb46f mem-cache: use MMU instead of TLB in prefetchers Nathanael Premillieu 2022-12-13 14:31:12 +01:00
• f7857867ae fastmodel: Export the "reset_in" reset signal from the PL330. Gabe Black 2023-01-12 01:05:32 -08:00
• 76b74fa51f util: use origin/develop as default upstream branch Giacomo Travaglini 2023-01-13 16:26:03 +00:00
• 899f702f12 configs: Start using the new CpuCluster class in example/arm Giacomo Travaglini 2022-10-25 09:31:10 +01:00
• 8149245ecc cpu: Formalize a CPU cluster class in the gem5 standard library Giacomo Travaglini 2022-10-24 17:28:06 +01:00
• 4954167fe5 mem: create port_wrapper classes Earl Ou 2023-01-04 19:48:18 -08:00
• a2658f08e5 systemc: fix -Wno-free-nonheap-object for building scheduler.cc Earl Ou 2023-01-10 00:27:53 -08:00
• a7ef5b77d6 mem: Implemement backdoor interface for Bridge Yu-hsin Wang 2023-01-11 13:19:10 +08:00
• 626e445563 dev: Add a "resetter" callback to the typed register class. Gabe Black 2023-01-10 05:02:05 -08:00
• 7c670c1667 arch-riscv: Correct interrupt order Roger Chang 2023-01-03 14:00:32 +08:00